Designing with Verilog

COURSE CODE: LANG-VERILOG

This course provides a thorough introduction to the Verilog language.

The emphasis is on:

Writing efficient hardware designs
Performing high-level HDL simulations
Employing structural, Register Transfer Level (RTL), and behavioral coding styles
Targeting AMD devices specifically and FPGA devices in general
Utilizing best coding practices

This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

Live Online Training (9am-5pm ET)

February 18-20, 2025 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Be the first to know. Sign up for our newsletter.

Who should attend:

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Software Tools

Vivado Design Suite

Hardware

Architecture: N/A*
Demo board: Zynq UltraScale+ MPSoC ZCU104 board*

* This course does not focus on any particular architecture.

Skills Gained

After completing this comprehensive training, you will know how to:

Write RTL Verilog code for synthesis
Write Verilog test fixtures for simulation
Create a finite state machine (FSM) by using Verilog
Target and optimize AMD FPGAs and adaptive SoCs by using Verilog
Use enhanced Verilog file I/O capabilities
Run a timing simulation by using AMD Simprim libraries
Create and manage designs within the Vivado Design Suite environment
Download to the evaluation demo board

Course Outline

Day 1	Day 2	Day 3
Introduction to Verilog Discusses the history of the Verilog language and provides anoverview of the different features of Verilog. {Lecture} Verilog Keywords and Identifiers Discusses the data objects that are available in the Verilog language as well as keywords and identifiers. {Lecture} Verilog Data Values and Number Representation Covers what data values are in Verilog, as well as how to represent numbers in Verilog. {Lecture} Verilog Data Types Covers the various data types in Verilog. {Lecture} Verilog Buses and Arrays Covers buses and arrays in Verilog. {Lecture} Verilog Modules and Ports Describes both the syntax and hierarchy for a Verilog module, port declarations, and the difference between reg versus wire. {Lecture, Demo, Lab} Verilog Operators Shows the syntax for all Verilog operators. {Lecture} Continuous Assignment Introduces the Verilog continuous assignment statement. {Lecture} Gate-Level Modeling Introduces gate-level modeling in Verilog {Lecture} Procedural Assignment Provides an introduction to procedural assignments in Verilog, including their usage and restrictions. {Lecture} Blocking and Non-Blocking Procedural Assignment Introduces blocking and non-blocking assignment statements in Verilog. {Lecture, Lab} Procedural Timing Control Introduces the timing control methods that are used in procedural assignments. {Lecture}	Verilog Control Structures: if-else Describes the if/else control structure. {Lecture, Lab} Verilog Control Structures: case Describes the case control structure. {Lecture} Verilog Loop Statements Introduces the different types of Verilog loop statements. {Lecture} Introduction to Verilog Testbenches Introduces the concept of the Verilog testbench {Lecture, Lab} System Tasks Provides a basic understanding of system tasks. {Lecture} Verilog Subprograms Covers the use of subprograms in verification and RTL code to model functional blocks. {Lecture} Verilog Functions Describes functions, which are integral to reusable and maintainable code. {Lecture} Verilog Tasks Covers tasks in Verilog. {Lecture} Verilog Compiler Directives Describes Verilog compiler directives. {Lecture} Verilog Parameters Covers Verilog parameters and the local parameter concept. {Lecture, Lab} Verilog Generate Statements Introduces the Verilog generate statement. {Lecture}	Timing Checks Covers the timing check statements in Verilog and talks about the specify block. {Lecture} Finite State Machines Provides an overview of finite state machines, one of the more commonly used circuits. {Lecture} Mealy Finite State Machine Describes the Mealy FSM and how to code for it. {Lecture, Lab} Moore Finite State Machine Describes the Moore FSM and how to code for it. {Lecture, Lab} FSM Coding Guidelines Shows how to model an FSM of any complexity in Verilog and describes recommendations for performance and reliability. {Lecture} Avoiding Race Conditions in Verilog Describe what a race condition is and provides steps to avoid this condition. {Lecture} File I/O: Introduction Covers using basic and enhanced Verilog file I/O capabilities for more robust design verification. {Lecture} File I/O: Read Functions Covers Verilog file I/O read capabilities. {Lecture, Lab} File I/O: Write Functions Covers Verilog file I/O write capabilities. {Lecture} Targeting AMD FPGAs and Adaptive SoCs Focuses on implementation and chip-level optimization specific to AMD devices. {Lecture, Lab} User-Defined Primitives Describes user-defined primitives (UDPs). {Lecture} Programming Language Interface Introduces the programming language interface (PLI) in Verilog. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic digital design knowledge

RELATED COURSES:

Updated 8-18-2024

©2024 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

Designing with Verilog