Designing with Versal AI Engine: Quick Start

COURSE CODE: AIE-QSTART

This course covers the AMD Versal™ AI Engine architecture and memory modules, programming the AI Engine (kernels and graphs), using the DSP Library, developing AI Engine designs using AMD Vitis™ Model Composer, and debugging the AI Engines.

The emphasis of this course is on:

Illustrating the AI Engine architecture and memory modules
Describing the Vitis and AI Engine tool flow
Programming the AI Engine with kernels and graphs
Describing the AI Engine APIs, including streaming data APIs, and I/O buffers
Utilizing the Vitis DSP library for AI Engines
Creating AI Engine designs using Vitis Model Composer
Describing the debugging methodology for AI Engines

See Course Outline

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$600	6
In-Person Registration - $600/day	$600	6
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee)	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

1 Day

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Be the first to know. Sign up for our newsletter.

Who should attend:

Software and hardware developers, system architects, DSP users, and anyone who needs to accelerate their software applications using our devices.

Software Tools

Vitis Unified IDE
Vitis Model Composer

Hardware

Architecture: Versal adaptive SoC

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe the AMD Versal adaptive SoC and the architecture of the AI Engine
Describe the toolchain for Versal AI Engine programming and the full application acceleration flow with the AMD Vitis Unified IDE
Program the AI Engines for single and multiple kernels using graphs
Describe the AI Engine APIs, including streaming data APIs, and I/O buffers that are used in programming
Utilize the AI Engine DSP library and create a filter design in the Vitis tool
Design a filter with the AMD Vitis Model Composer AI Engine library
Describe the debug methodology available for AI Engines

Course Outline

Day 1
Versal AI Engine Architecture Introduction to the AMD Versal AI Engine Architecture Describes the Versal adaptive SoC at a high level. Also introduces the architecture of the AI Engine and its memory modules and interfaces. {Lecture} Vitis Tool Flow Versal AI Engine Tool Flow Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Labs} The Programming Model AI Engine Programming: Kernels and Graphs Investigates AI Engine kernels and Adaptive Data Flow (ADF) graphs along with their programming flows. {Lecture, Lab} Introduction to the APIs and Data Access Mechanisms Describes the AI Engine APIs for loading and storing data as well as the I/O buffers and streaming data APIs that are used in programming data access mechanisms. {Lecture} Libraries AI Engine DSP Library Overview Provides an overview of the available DSP library, which enables faster development and comes with ready-to-use example design that help with using the library and tools. {Lecture, Lab} Vitis Model Composer Vitis Model Composer for AI Engine Design Describes the Vitis Model Composer tool and how to use the libraries available with the tool for AI Engine design development. {Lecture, Lab} Debugging Versal AI Engine Application Debug and Event Trace Reviews the debugging methodology for AI Engine designs. {Lecture}

Day 1

Versal AI Engine Architecture
Introduction to the AMD Versal AI Engine Architecture
Describes the Versal adaptive SoC at a high level. Also introduces the architecture of the AI Engine and its memory modules and interfaces. {Lecture}

Vitis Tool Flow
Versal AI Engine Tool Flow
Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Labs}

The Programming Model
AI Engine Programming: Kernels and Graphs
Investigates AI Engine kernels and Adaptive Data Flow (ADF) graphs along with their programming flows. {Lecture, Lab}

Introduction to the APIs and Data Access Mechanisms
Describes the AI Engine APIs for loading and storing data as well as the I/O buffers and streaming data APIs that are used in programming data access mechanisms. {Lecture}

Libraries
AI Engine DSP Library Overview
Provides an overview of the available DSP library, which enables faster development and comes with ready-to-use example design that help with using the library and tools. {Lecture, Lab}

Vitis Model Composer
Vitis Model Composer for AI Engine Design
Describes the Vitis Model Composer tool and how to use the libraries available with the tool for AI Engine design development. {Lecture, Lab}

Debugging
Versal AI Engine Application Debug and Event Trace
Reviews the debugging methodology for AI Engine designs. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Comfort with the C/C++ programming language
Software development flow
Vitis tool for application acceleration development flow

RELATED COURSES:

Updated 08-29-2025

©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.