Designing with the IP Integrator Tool

COURSE CODE: FPGA-IPI

Explore the AMD Vivado IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IP integrator block designs using the AMD Vivado Design Suite.

This course focuses on:

Creating an IP integrator block design using the Vivado Design Suite
Creating your own custom IP via the IP packaging flow
Using the block design container (BDC) and module referencing features of the IP integrator
Using the IP integrator to add and configure the Versal™ device CIPS block and then to export the generated programmable device image (PDI)
Configuring the AXI network on chip (NoC) to access DDR memory controllers in Versal devices

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

3 Days

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

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Who should attend:

Software and hardware developers, system architects, and anyone who wants to learn about the Vivado Design Suite IP integrator tool.

Software Tools

Vivado Design Suite 2024.1
Vitis Unified IDE 2024.1

Hardware

Architecture: UltraScale family and Versal adaptive SoCs
Demo board: Zynq UltraScale+ ZCU104 board

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe the Vivado tool flow for RTL-based and IP-based design flows
Create a Vivado IP integrator block design using the Vivado Design Suite
Describe the block design container feature in the IP integrator
Package custom IP and add it to the IP catalog repository or manage it from a remote location
Add an RTL module or a block design (BD) into a block design by using RTL module referencing
Add and configure the Versal device CIPS block and export the generated hardware
Configure the AXI NoC to access DDR memory controllers in Versal devices
Debug a design by adding debug cores using the IP integrator
Use a revision control system in the Vivado Design Suite flows

Course Outline

Day 1	Day 2	Day 3
Vivado IP Catalog Vivado IP Flow Demonstrates how to customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo} Using the Vivado IP Integrator Getting Started with Vivado IP Integrator Introduces the Vivado IP integrator tool and its features. Also reviews creating and working with block designs. {Lecture, Demo, Lab} Designing IP Subsystems Using Vivado IP Integrator Illustrates designing with processor-based subsystems and working with custom RTL code. Also explains how to create Vitis platforms using Vivado IP integrator. {Lecture, Lab} Block Design Containers in the Vivado IP Integrator Describes the block design container feature and how BDCs enable DFX. {Lecture, Lab}	Creating and Packaging Custom IP Covers creating your own IP and package and including it in the Vivado IP catalog. {Lecture, Lab} Module Referencing in IP Integrator Shows how to quickly add an RTL module or a block design (BD) into a block design by using RTL module referencing. {Lab} Versal Adaptive SoC: Hardware Platform Development Using the Vivado IP Integrator Describes the different Versal device design flows and covers the platform creation process using the Vivado IP integrator. {Lecture, Lab} Versal Adaptive SoC: NoC Introduction and Concepts Reviews the basic vocabulary and high-level operations of the NoC. {Lecture, Labs}	Debugging Debug Flow in an IP Integrator Block Design Shows how to insert the debug cores into IP integrator block designs. {Lecture, Lab} Version Control Systems Revision Control Systems in the Vivado Design Suite Investigates using version control systems with the Vivado design flows. {Lecture, Lab} Vivado IP Catalog Managing IP in Remote Locations Covers storing IP and related files that are remote to the current working project directory. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of AMD FPGAs and adaptive SoCs

RELATED COURSES:

Updated 08-29-2025

©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

Designing with the IP Integrator Tool