Vivado Quick Start with Versal Devices Workshop
Vivado Quick Start with Versal Devices Workshop
This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs.
The emphasis of this course is on:
- Introduction to designing FPGAs with the Vivado Design Suite
- Creating a Vivado project with source files
- Introduction to the Tcl environment in Vivado and its importance
- Using the Vivado IP Integrator
- Synthesizing and implementing
- Generating and downloading a bitstream onto a demo board
- Understanding AMD devices
This course focuses on the Versal adaptive SoC architecture.
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
SCHEDULED EVENTS
Training Duration:
1 Day (6 hours)
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Who should attend:
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite and digital designers who have a working knowledge of HDL (VHDL or Verilog) but are new to AMD FPGAs and adaptive SoCs.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Use the New Project Wizard to create a new Vivado IDE project
- Describe the supported design flows of the Vivado IDE
- Synthesize and implement an HDL design
- Create a Tcl script to create a project, add sources, and implement a design
- Use the Vivado IP integrator to create a block design
- Describe the AMD Versal adaptive SoC architecture
Course Outline
| Day 1 |
|---|
| Introduction to the Vivado Design Suite Describes various design flows and the role of the Vivado IDE in the flows. Introduction to the Tcl Environment Introduces Tcl (tool command language). Vivado IP Flow Demonstrates how to customize IP, instantiate IP, and verify the hierarchy of your design IP. Vivado Synthesis and Implementation and Bitstream Generation Reviews creating timing constraints according to the design scenario, synthesizing and implementing the design, and, optionally, generating and downloading a bitstream to a demo board. Getting Started with Vivado IP Integrator Introduces the Vivado IP integrator tool and its features. Also reviews creating and working with block designs. Designing IP Subsystems Using Vivado IP Integrator Illustrates designing with processor-based subsystems and working with custom RTL code. Also explains how to create Vitis™ platforms using Vivado IP integrator. AMD FPGA and Adaptive SoC Portfolio Introduces 7 series and UltraScale FPGAs, stacked silicon interconnect-based 3D IC devices, Zynq 7000 SoCs, Zynq UltraScale+ MPSoCs, and Versal™ adaptive SoCs. DEMO: Vivado Design Suite Project-Based Mode DEMO: Creating an IP Core on a Versal Device DEMO: Vivado Synthesis and Implementation |
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic knowledge of the VHDL or Verilog language
- Digital design knowledge