Versal Adaptive SoCs Quick Start Workshop: A Guide to Integration and Implementation
Versal Adaptive SoCs Quick Start Workshop: A Guide to Integration and Implementation
BLT Engineers have successfully deployed designs to Versal devices for Clients. Learn from the experts.
This 4-hour online workshop explores the AMD Versal adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge of embedded software development and application partitioning. Also learn how to perform system migration to the Versal architecture.
The emphasis of this course is on:
- Reviewing the architecture of the Versal adaptive SoC
- Describing the different engines available in the Versal architecture and what resources they contain
- Demonstrating the embedded software development flow for Versal devices
- Describing the architectures of the network on chip (NoC) and AI Engine
- Explaining application partitioning based on the models of computation
- Comparing various functional blocks of the Versal devices to previous-generation devices
This course focuses on the Versal adaptive SoC architecture.
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
SCHEDULED EVENTS
Training Duration:
1 Day (4 hours)
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Who should attend:
Software and hardware developers, system architects, and anyone who wants to learn about the architecture and programming of the Versal adaptive SoC.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Describe the AMD Versal architecture
- Describe the Versal design flows
- Describe the embedded software development flow for Versal devices
- Design using the network on chip (NoC)
- Create a simple AI Engine application
- Follow the high-level system migration recommendations provided in this course
Course Outline
| Day 1 |
|---|
| Architecture Overview Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture. {Lecture} Design Tool Flow Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly. Embedded Software Development Describes the software development environments and embedded software development flows for Versal devices. Also introduces embedded software debugging. NoC Introduction and Concepts Covers the reasons to use the network on chip, its basic elements, and common terminology. AI Engine Discusses the AI Engine array architecture, terminology, and AI Engine interfaces. Application Partitioning 1 Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed. System Migration Compares the various functional blocks of the Versal devices to previous-generation devices. Describes the migration of designs from the UltraScale and UltraScale+ architectures to the Versal architecture. DEMO: Design Tool Flow DEMO: Embedded Software Development DEMO: NoC Introduction DEMO: AI Engine Introduction |
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic knowledge of AMD FPGAs and adaptive SoCs
- Basic knowledge of the Vivado and Vitis tools
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