Xilinx for Managers
Xilinx for Managers
Managers of FPGA-based programs are under constant pressure to produce quality results and have little (no) time to reinvent the wheel or deal with problems that are avoidable. Recognizing and mitigating risk, understanding how schedules might be accelerated and dealing with and avoiding problems and additional costs are just a few areas which can put us out of our comfort zone... Especially when dealing with new technologies.
Xilinx for Managers is designed to address these issues. BLT has been involved with hundreds of FPGA/SoC designs over three decades and has directed the efforts of hundreds of engineers. We'll teach you how to accelerate your projects and turn the black art of FPGA/SoCs into a straightforward discipline.
While BLT's other courses are targeted at hard-core engineers, expanding and deepening their knowledge, this course offers a management perspective.
Attendees also have ample opportunities to network with other managers who share similar challenges.
For FPGA/SoC-based projects, management's commitment to methodology can truly make or break a project's schedule or budget. With the right knowledge, as a manager, you can really make a difference.
After completing this comprehensive training, you will know how to:
- Know 5 essential elements of effective FPGA/SoC design - BLT's PSSST approach
- Know how to employ a disciplined methodology to manage FPGA/SoC-based designs
- Know how to Architect, specify and plan FPGA/SoC-based projects
- Understand how Xilinx tools are employed
- Understand the various Xilinx FPGA and SoC families, their overall functionality and capabilities
- Be better able to assess an engineering candidate's ability to effectively design with FPGA/SoCs
- Be better able to develop design teams to implement Xilinx FPGA/SoCs most effectively
- Be better able to estimate Chip size and cost as early as practical
- Appreciate common FPGA/SoC design challenges and know how to best address them
- Recognize and mitigate risk factors to a project's schedule and cost
- Cut through seemingly complex problems to stay on track
- Get help when your internal resources are struggling
- Xilinx Silicon Solutions
- Xilinx Development Tools
- FPGA Project Management
- FPGA Fabric Design
- SoC Design
- Best Practices
- Open Discussion
No Scheduled Sessions - Contact Us to ask about setting one up!
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Who should attend:
Managers who need to get FPGA/SoC-based projects completed on time and on budget
This course is for managers and Lead-Engineers leading FPGA/SoC-based development efforts.
This is NOT the course for you if you need to know, from the ground up, how to architect, enter, implement, simulate and verify Xilinx FPGAs, this course is NOT going to teach you these skills. Please contact BLT so we can address and tailor a learning plan, including languages, tools and silicon training, to meet your specific needs.
Vivado™ (the sucessor to ISE) - Xilinx's integrated design environment (IDE) which provides the ability to design, verify and implement FPGAs and SOCs in an accelerated timeframe.