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BLT Technology Summit 2024 – Embedded and Programmable Solutions

Are you struggling with timing issues, migration complexities, or performance bottlenecks that cause costly delays and frustrations? The BLT Technology Summit 2024 tackles these head-on with expert-led sessions designed to provide you with actionable solutions. Whether it’s accessing Versal resources, simplifying FPGA timing reports, or avoiding common design failures, this event will equip you with the knowledge to overcome these challenges and eliminate costly delays.

This one-day, in-person event features expert-led sessions and live demos. Ideal for hardware engineers, embedded software developers, system architects, and managers. Meet and consult with industry peers, including our BLT experts and AMD personnel.

Select your location below to register. For questions, please call 888-945-4691.

One Event, Three Locations:

Orlando, FL

October 22, 2024

Melbourne, FL

October 24, 2024

Columbia, MD

October 29, 2024

Event Details

  • One-day event, 10 am – 4 pm
  • Check-in opens at 9 am
  • Breakfast, lunch, parking included
  • Price: $100 per person or 2 AMD Training Credits

Who Should Attend?

  • Hardware Engineers
  • Embedded Software Developers
  • System Architects
  • Engineering and Program Managers

2024 Agenda:

TIMESESSION TOPIC
9:00 - 10:00 amRegistration & Breakfast
10:00 - 10:10 amOpening Remarks
10:10 - 11:00 amGo NoC or Go Home: The ONLY Way to Access Key Versal Resources

Do you know how to interface with the Versal NoC, configure dozens of pages in the NoC's configuration wizard(s), connect to DDR, or use ChipScoPy to accelerate debugging? The Versal NoC is the silver bullet for routing challenges. Learn how to solve your latency, bandwidth, routing and resource allocation issues, and when NOT to use the NoC. Includes a lecture and demo.
11:00 - 11:30 amSession Presented by AMD
11:30 - 12:00 pmAXI Nightmares: Avoid and Debug Performance Bottlenecks

Frustrated tracing bugs in AXI’s concurrent transactions? Does out-of-order data make debugging feel like finding a needle in a haystack? Get to the bottom of performance issues and arbitration delays in your AXI implementation and take the complexity out of AXI. Includes a lecture and a demo.
12:00 - 1:00 pmLunch
1:00 - 1:40 pmMigration Frustration: Navigating Steep Learning Curves with New FPGA Architectures and Tools

Is the fear of unknown risks and costs keeping you from migrating to newer devices? (Even if you have to?) Are you stressed about new and constantly evolving tools and technologies but need to migrate for higher performance, availability, bandwidth, and latency? Learn about common issues in migration, from IO clocking, transceivers, voltages, configurations, booting, and more. Also hear about common issues when migrating between like devices. Includes a lecture and a demo.
1:40 - 2:20 pmBack to Vivado Flow: Marty, This Is the Future

The Vitis Export to Vivado Flow turbocharges your SW/HW team collaboration and productivity. Are you a HW engineer with minimal visibility into SW development? Are you a SW engineer with limited visibility into HW development? This new feature for Vivado 2024.1 helps compress schedules and reduce team frustrations. Includes a lecture and demo.
2:20 - 2:30 pmBreak
2:30 - 3:10 pmConfronting FPGA Timing Failures and Cracking the Secrets of Complex Timing Reports

Are you still getting timing errors even after you've added all your timing constraints? Does it take overnight for the tools to try to meet timing? Learn the specifics of timing closure and how to read and leverage a timing report. Includes a lecture and demo.
3:10 - 3:50 pm5 Reasons FPGA Designs Fail: How to Prevent Them and Costly Delays

Are you finding bugs on the bench? Afraid you might not be catching them all? When simulation doesn't meet reality, it's usually one of 5 reasons. Learn what they are and how to prevent costly surprises and unpredictable outcomes. Includes a lecture and demo.
3:50 - 4:00 pmClosing Remarks
4:00 - 4:30 pmNetworking Opportunity
BLT is an AMD Premier Partner for Design Services.