BLT Adaptive Computing Summit

Join your colleagues and the experts from BLT and the AMD Xilinx Adaptive and Embedded Computing Group for this in-person event discussing emerging technologies and solutions. Learn about the latest in SoC tools, technologies and cutting-edge solutions, from RFSoCs to Versal Adaptive SoCs (formerly called Versal ACAPs).

We’re offering this event in three locations throughout the Southeast: Melbourne, FL; Orlando, FL; Huntsville, AL; as well as at BLT’s headquarters in Columbia, MD. The event includes 8 sessions, hot buffet breakfast, hot buffet lunch, beverages, snacks, and a networking reception with hors d’oeuvres. Select your location below to register. For questions, please call 888-945-4691.

Space is limited. Reserve your spot now for this exclusive event.

AMD is the official sponsor of this event.

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One Event, Four Locations:

Columbia, MD

April 25, 2023

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Melbourne, FL

May 2, 2023

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Orlando, FL

May 4, 2023

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Huntsville, AL

May 17, 2023

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Summit Agenda

All times are local to the event.

TIME	SESSION
8:00 - 9:00	Registration & Breakfast
9:00 - 9:15	Opening Remarks
9:15 - 10:00	RFSoC Case Study: SAR on Orbit Low-Voltage IO for defense grade parts and considerations when using DDR4 Reliable and Safe State Machines for LEO Introduction to SAR and the benefits of a space-based approach
10:00 - 10:30	An Introduction to Versal, presented by AMD
10:30 - 10:45	Break
10:45 - 11:30	Common DSP Function Benchmarks (FIR, FFT and Matrix) – AIE vs. PL
11:30-12:00	Managing FPGA & SoC Projects: The Methodologies Behind BLT's Secrets to Success BLT's design methodologies for successful projects on the first try, every time How to make the tools work efficiently and quickly on large designs
12:00 -1:00	Lunch
1:00 - 1:30	STAP Radar design – development flow and results
1:30 - 2:15	Versal Channelizer Benchmark (AI vs PL) A comparison of results when implementing in Programmable Logic vs AI Engines Expectations on power consumption Trade-study between each approach
2:15 - 2:30	Break
2:30 - 3:00	DEMO: Cross Triggering Is Your (Powerful) Friend Tips and tricks for debugging SoCs and systems which contain software and programmable logic Live Demonstration which shows engineers how to enable this capability for their designs
3:00-3:30	System mapping Tool – Deciding what goes in AIE and what goes in DSP58 (Versal)
3:30 - 4:00	Engineering Roundtable Panel of Experts will provide valuable information and answer audience questions Space, Security, or DFX (topic dependent on location) Advanced Debugging Tips & Tricks for FPGA and SoC design
4:00	Closing Remarks
4:00 - 5:00	Networking Reception

Event Details

One-day event, 8 am – 5 pm
Breakfast, lunch, beverages included
Limited space – up to 100 attendees
$199 advanced pricing, $299 after

Who Should Attend?

Hardware Engineers
Embedded Software Developers
System Architects
Engineering Managers

About BLT Training

BLT has been offering AMD Xilinx training for more than 25 years.

We’ve trained thousands engineers in the methodology, subtleties, rigors and art of FPGA design.
We specialize in AMD Xilinx FPGA training courses, but also offer custom classes.
BLT training is taught by BLT’s Design Services engineers that bring their real-world knowledge to enhance the training experience.

Why BLT Training is different:

We offer office hours to help with pre-class setup.
We have multiple lab instructors for larger classes.
No cancellations for online classes.

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BLT Adaptive Computing Summit