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When engineers compare HDLs, the discussion often starts with Verilog versus VHDL. But within the Verilog family itself, there is another important distinction worth understanding. Verilog vs SystemVerilog... they are not competing languages with separate roles. SystemVerilog is an evolution of Verilog that encompasses both design and verification. Understanding how these languages relate to one … Continued

This fall took us to two AMD Security Working Group events: first to Colorado in October, then to Washington, DC in November. After decades of working with AMD, these SWG events have become some of our favorite gatherings of the year. There's something special about being in a room with people who truly understand what's … Continued

AI is making waves in engineering, and FPGA & embedded hardware teams are no exception. From automating routine tasks to speeding up research, AI can be a powerful assistant, but it’s not a substitute for deep expertise. In FPGA and hardware projects, where stakes are high and timelines are tight, understanding where AI helps — … Continued

BLT’s expert SME (subject matter experts) engineers were recently the instructors for the AMD Regional Technical Training event (RTT) in Longmont, Colorado. It was a weeklong, closed event for AMD, Avnet (an AMD distributor), and AMD Premier Partners. Throughout the week, participants collaborated on the latest AMD technologies, tools, and workflows. As part of the … Continued

We’re thrilled to announce that BLT has officially joined the Microchip Design Partner Program as a Design Partner. You can read our Press Release about it here: BLT Joins Microchip Partner Program For more than three decades, BLT has delivered custom electronics for aerospace, space, defense, and intelligence clients. We have decades of design experience … Continued

Efficiently moving large amounts of data between the processing system, AI Engines, and programmable logic is a core capability of modern FPGA designs and a challenge for today’s engineers designing with them. The AMD Versal architecture accomplishes this with a dedicated Network on Chip (NoC), enabling high-speed, deterministic communication, including direct access to DDR memory … Continued

A Lookup Table (LUT) is a data structure or hardware component that maps input values to output values. Instead of performing a calculation repeatedly, a LUT enables you to store the results of those calculations in advance and simply “look them up” when needed. This can save significant time and computational resources, especially in systems … Continued

Synthetic Aperture Radar (SAR) works by moving the Aperture (antenna) through space and compiling a result based on a compilation of the varying views of the data captured. As such, SAR processing involves demanding, high-throughput computations, especially when resolution, latency, and scalability are critical. To demonstrate what’s possible with the AMD Versal Adaptive SoC, AMD … Continued

When debugging FPGA designs, simple triggers often don’t cut it. Complex designs frequently require capturing data only after a specific sequence of events or when multiple signals meet intricate conditions. This is where advanced triggering with trigger state machines (TSMs) comes into play, giving engineers powerful control over when and how data capture starts within … Continued