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FPGA Resets

FPGA Resets – Strategies Designers Should Know

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Don’t underestimate the reset. Assert reset, clear state, move on. In practice, resets are one of the common sources of unpredictable behavior in FPGA designs. A design that works perfectly in simulation can behave very differently on real hardware if the reset strategy is poorly thought out. Getting resets right requires stepping back and thinking … Continued
multi-bit CDCs

Optimizing Multi-Bit CDCs and Bus Skew with Vivado Reports

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In complex FPGA designs, engineers often work with multi-bit signals that cross clock domains (CDCs). Handling these correctly is critical to prevent data corruption. AMD Vivado provides reports such as CDC and Bus Skew to help engineers verify and optimize these paths. Types of Clock Relationships for Multi-bit CDCs Unlike single-bit signals, multi-bit CDCs carry … Continued
AMD Vivado Report CDC Clock Domain Crossings

Using the Vivado CDC Report to Verify Clock Domain Crossings

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In modern FPGA designs, multiple clock domains are common, and signals often cross from one domain to another. These clock domain crossings (CDC) are critical points where timing issues that cause metastability can occur. The AMD Vivado CDC Report helps engineers identify and verify these crossings, ensuring robust and predictable designs. What the Vivado CDC … Continued

Debugging Embedded Software on FPGA Platforms

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Debugging embedded software on FPGA‑based systems is uniquely challenging because you’re often dealing with tightly coupled hardware and software interactions across programmable logic (PL) and one or more processing systems (PS). On platforms such as the AMD Zynq UltraScale+ MPSoC and Versal adaptive SoC devices, effective debug flows combine software debuggers, hardware monitors, and system‑level … Continued
AMD Embedded x86 Processors

How AMD Embedded x86 Processors Fit Into Real-World Systems

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When most people hear “x86 processor,” they think laptops, desktops, or cloud servers. But there’s a category of x86 embedded devices built for something very different: long-lived, rugged systems that operate in factories, telecom racks, vehicles, and secure facilities for long-term use. The AMD Embedded x86 portfolio exists for those systems. If you’re designing an … Continued
BLT Named AMD Partner of Year

AMD Partner of the Year and Training Provider of the Year Announcement

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BLT Awarded Unprecedented Dual AMD Partner of the Year Honors BLT is honored to announce it has been recognized by AMD with its two highest partner honors: AMD Premier Embedded Partner of the Year and AMD Outstanding Authorized Training Provider (Large) of the Year. This marks a historic first within the AMD partner ecosystem, as … Continued
EDF vs Yocto

PetaLinux vs EDF vs Yocto: Where to Go Next?

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As AMD officially moves away from PetaLinux, new development within the AMD ecosystem is moving toward the Embedded Developer's Framework (EDF) and Yocto-based workflows. For engineering teams, this isn’t just the end of a tool but a shift in embedded Linux development practices that could affect future designs. So, what now? How do you pick … Continued
AMD Vivado vs Vitis

Vivado vs Vitis IDE: When to Use Which Tool in AMD FPGA and SoC Development

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Working with AMD adaptive SoCs and FPGAs requires navigating two key tools: Vivado Design Suite and the Vitis Integrated Design Environment (IDE). Both are essential to modern development, but each serves a distinct purpose. Understanding the roles of Vivado vs Vitis helps streamline workflows, prevent confusion, and ensure your design process is efficient. Vivado Design … Continued
Modular Design

Modular Design in Verilog and VHDL: How to Build Reusable IP

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"Don’t reinvent the wheel." Seems simple enough. Unfortunately, it is all too common that a new project, in general, will involve redoing the same things. You might say, "I need a SPI interface." "I need a register space," or "I need some module with a slight modification from previous designs." Many times, this can be … Continued
Vivado Utilization Report

Understanding the Vivado Utilization Report

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As FPGA designs grow in complexity, understanding how device resources are being used becomes increasingly important. Even designs that meet timing can run into issues if resources are overutilized or unevenly distributed. The Vivado Utilization Report in the AMD Vivado Design Suite provides a detailed breakdown of how the design maps onto the target device. … Continued

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