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As AMD officially moves away from PetaLinux, new development within the AMD ecosystem is moving toward the Embedded Developer's Framework (EDF) and Yocto-based workflows. For engineering teams, this isn’t just the end of a tool but a shift in embedded Linux development practices that could affect future designs. So, what now? How do you pick … Continued

Working with AMD adaptive SoCs and FPGAs requires navigating two key tools: Vivado Design Suite and the Vitis Integrated Design Environment (IDE). Both are essential to modern development, but each serves a distinct purpose. Understanding the roles of Vivado vs Vitis helps streamline workflows, prevent confusion, and ensure your design process is efficient. Vivado Design … Continued

"Don’t reinvent the wheel." Seems simple enough. Unfortunately, it is all too common that a new project, in general, will involve redoing the same things. You might say, "I need a SPI interface." "I need a register space," or "I need some module with a slight modification from previous designs." Many times, this can be … Continued

As FPGA designs grow in complexity, understanding how device resources are being used becomes increasingly important. Even designs that meet timing can run into issues if resources are overutilized or unevenly distributed. The Vivado Utilization Report in the AMD Vivado Design Suite provides a detailed breakdown of how the design maps onto the target device. … Continued

In embedded systems and electronics design, the terms FPGA and SoC are often used interchangeably, but understanding fpga vs soc is essential because they describe fundamentally different types of hardware. Understanding the distinction is crucial for engineers, program managers, and decision-makers designing high-performance or mission-critical systems. What Is an FPGA? FPGA stands for Field-Programmable Gate … Continued

Bugs are cheapest when they are caught early. Once they escape into synthesis, timing closure, or—worse—hardware, they become expensive lessons. Your first and best opportunity to catch them is not in the lab, but in simulation. That makes the testbench your first line of defense. Unfortunately, testbenches are often treated as disposable. Something quick is … Continued

Issues with clock domains are among the most common—and most expensive—problems in digital design. They rarely announce themselves clearly. Instead, they hide behind intermittent failures, lab-only bugs, or timing violations that appear and disappear with small changes. A design might simulate perfectly and may even work on the bench most of the time, only to … Continued