Vitis FastTrack: Session 3 – System Debug

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

BLT’s Vitis FastTrack series demonstrates the tools and techniques required for both software and hardware accelerated design using the Vitis Unified Software platform.

Learn how Vitis helps accelerate C, C++, and AI applications for cloud, edge, and embedded designs in a single suite. Learn how to migrate existing SDK projects and develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis unified software environment targeting both embedded and cloud applications.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Implement an effective software design environment for a Xilinx embedded system using the Vitis unified software platform
  • Describe how the FPGA architecture lends itself to parallel computing
  • Understand how to optimize AI models for deployment on an FPGA platform using Vitis AI
  • Explain how the Vitis unified software environment helps software developers focus on application
  • Accelerate C, C++, and RTL using the RTL Kernel Wizard
  • Debug applications running on embedded systems using Vitis

Course Outline

Session 1

  • Introduction to Hardware Acceleration
  • Vitis Software Accelerated Libraries
  • Introduction to the Vitis Unified Software Platform
  • Vitis IDE Tool Flow -> Vitis Command Line Flow
  • For pricing and other scheduled sessions see
    Vitis FastTrack Series

Session 2

  • Overview of ML Concepts
  • Frameworks supported by Vitis AI
  • Introduction to the Deep Learning Processor
  • AI Quantizer and AI Compiler
  • Vitis AI Library
  • For pricing and other scheduled sessions see
    Vitis FastTrack Series

Session 3

  • Driving the Vitis Software Development Tool
  • Migrating from SDK to Vitis
  • System Debugger
  • For pricing and other scheduled sessions see
    Vitis FastTrack Series

No Scheduled Sessions – Contact Us to ask about setting one up!

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Training Duration:

3 Hours

Who should attend:

  • Designers looking to migrate existing designs to the Vitis platform
  • Developers interested in using FPGAs to accelerate AI inference in the cloud or on the edge
  • Software engineers looking to accelerate C, C++, and RTL solutions using Vitis and FPGAs.

Prerequisites:

Version: 2021-03-17_0932