Versal Adaptive SoC Design Methodologies Workshop
Versal Adaptive SoC Design Methodologies Workshop
BLT Engineers have successfully deployed designs to Versal devices for Clients. Learn from the experts.
This online workshop explores using different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn about application partitioning to enhance the performance of a design.
The emphasis of this course is on:
- Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
- Creating a custom extensible platform from AMD Vivado
- Providing an overview of the embedded software development flow for Versal devices
This course focuses on the Versal adaptive SoC architecture.
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
SCHEDULED EVENTS
Training Duration:
1 Day
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Who should attend:
Software and hardware developers, system architects, and anyone who wants to learn about the Versal adaptive SoC design methodologies.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Describe the embedded software development flow for AMD Versal devices
- Use the provided design tools and Versal adaptive SoC design methodologies to create complex systems
- Create a custom AMD Vitis platform to run acceleration applications
Course Outline
| Day 1 |
|---|
| Hardware, IP, and Platform Development Methodology Describes the different Versal device design flows and covers the custom platform creation process using the Vivado IP integrator, RTL, HLS, and Vitis environment. Embedded Software Development Describes the software development environments and embedded software development flows for Versal devices. Also introduces embedded software debugging. DEMO: Hardware, IP, and Platform Development Methodology DEMO: Software Build Flow DEMO: Debugging DEMO: System Simulation |
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic knowledge of AMD FPGAs and adaptive SoCs
- Basic knowledge of the Vivado and Vitis tools