Designing with Xilinx Serial Transceivers

COURSE CODE: CONN-TRX

Learn how to employ serial transceivers in UltraScale and UltraScale+ FPGA designs or Zynq UltraScale+ MPSoC designs.

The focus is on:

Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection
Utilizing the Transceivers Wizards to instantiate transceiver primitives
Synthesizing and implementing transceiver designs
Taking into account board design as it relates to the transceivers
Testing and debugging

Learn more about Xilinx serial transceivers.

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1200	12
In-Person Public Registration - $600/day	$1200	12
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee)	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

2 Days

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

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Who should attend:

FPGA designers and logic designers.

Skills Gained

After completing this comprehensive training, you will know how to:

Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
Effectively utilize the following features of the gigabit transceivers:64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding, pre-emphasis and receive equalization
Use the Transceivers Wizards to instantiate GT primitives in a design
Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
Use the IBERT design to verify transceiver links on real hardware

Course Outline

Day 1	Day 2
UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Overview {Lecture} UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Clocking and Resets {Lecture} Transceiver IP Generation – Transceiver Wizard {Lecture} Lab 1: Transceiver Core Generation Transceiver Core Generation – Use the Transceivers Wizard to create instantiation templates. Transceiver Simulation {Lecture} Lab 2: Transceiver Simulation Transceiver Simulation – Simulate the transceiver IP by using the IP example design. PCS Layer General Functionality {Lecture} PCS Layer Encoding {Lecture} Lab 3: 64B/66B Encoding 64B/66B Encoding – Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.	Transceiver Implementation {Lecture} Lab 4: Transceiver Implementation Transceiver Implementation – Implement the transceiver IP by using the IP example design. PMA Layer Details {Lecture} PMA Layer Optimization {Lecture} Lab 5: IBERT Design IBERT Design – Verify transceiver links on real hardware. Transceiver Test and Debugging {Lecture} Lab 6: Transceiver Debugging Transceiver Debugging – Debug transceiver links. Transceiver Board Design Considerations {Lecture} Transceiver Application Examples {Lecture}

Day 1

Day 2

UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Overview {Lecture}

UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Clocking and Resets {Lecture}

Transceiver IP Generation – Transceiver Wizard {Lecture}

Lab 1: Transceiver Core Generation
Transceiver Core Generation – Use the Transceivers Wizard to create instantiation templates.

Transceiver Simulation {Lecture}

Lab 2: Transceiver Simulation
Transceiver Simulation – Simulate the transceiver IP by using the IP example design.

PCS Layer General Functionality {Lecture}

PCS Layer Encoding {Lecture}

Lab 3: 64B/66B Encoding
64B/66B Encoding – Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.

Transceiver Implementation {Lecture}

Lab 4: Transceiver Implementation
Transceiver Implementation – Implement the transceiver IP by using the IP example design.

PMA Layer Details {Lecture}

PMA Layer Optimization {Lecture}

Lab 5: IBERT Design
IBERT Design – Verify transceiver links on real hardware.

Transceiver Test and Debugging {Lecture}

Lab 6: Transceiver Debugging
Transceiver Debugging – Debug transceiver links.

Transceiver Board Design Considerations {Lecture}

Transceiver Application Examples {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Verilog experience (or the Designing with Verilog or the Designing with VHDL course)
Familiarity with logic design (state machines and synchronous design)
Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

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Updated 12-26-2024

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