Author: BLT Inc

lookup table LUT

What is a Lookup Table (LUT)?

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A Lookup Table (LUT) is a data structure or hardware component that maps input values to output values. Instead of performing a calculation repeatedly, a LUT enables you to store the results of those calculations in advance and simply “look them up” when needed. This can save significant time and computational resources, especially in systems … Continued
BLT SAR AI Engine Implementation with Versal VCK190

BLT AI Engine Implementation for SAR on AMD Versal VCK190

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Synthetic Aperture Radar (SAR) works by moving the Aperture (antenna) through space and compiling a result based on a compilation of the varying views of the data captured. As such, SAR processing involves demanding, high-throughput computations, especially when resolution, latency, and scalability are critical. To demonstrate what’s possible with the AMD Versal Adaptive SoC, AMD … Continued

Mastering Advanced Triggering with Trigger State Machines in ILAs

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When debugging FPGA designs, simple triggers often don’t cut it. Complex designs frequently require capturing data only after a specific sequence of events or when multiple signals meet intricate conditions. This is where advanced triggering with trigger state machines (TSMs) comes into play, giving engineers powerful control over when and how data capture starts within … Continued

What Is PCIe?

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What is PCIe? PCI Express (PCIe) is a high-speed serial interface used to connect processors and peripherals in everything from servers and workstations to embedded systems and FPGAs. If your system needs to move a lot of data fast, it is likely the protocol that makes it happen. PCI stands for Peripheral Component Interconnect in … Continued

Using QEMU with PetaLinux and Vitis for Embedded Software Development

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QEMU is a powerful emulation tool that enables early software debugging for complex SoCs like the AMD Zynq UltraScale+ MPSoC, without the need for physical hardware. When paired with PetaLinux and the AMD Vitis development environment, QEMU creates an efficient workflow for embedded Linux development and debugging. This post explains what these tools are, how … Continued

BLT Attends Microchip FPGA Tech Day: Diving Deep into FPGA Innovations

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Staying at the forefront of embedded systems and FPGA design requires more than just experience. It demands continuous learning and real-time engagement with the latest technologies. That’s why, at BLT, we make it a point to attend key industry events that give us access to the tools, techniques, and innovations shaping tomorrow’s solutions. This week, … Continued

Verilog vs VHDL: Choosing the Right HDL for FPGA Design

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The two dominant hardware description languages (HDLs), Verilog and VHDL, are both well-established, widely supported, and capable of describing complex digital systems. While each language can be used to create functionally identical hardware, they differ significantly in syntax, style, and design philosophy. When developing FPGA designs, selecting the right HDL is one of the first … Continued

Demystifying I/O Timing Constraints

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I/O timing constraints can be daunting, even for experienced FPGA designers. A common misconception is that these constraints somehow fix skewed input signals. They don’t. While synthesis and implementation tools can tolerate some signal misalignment, constraints are always required to determine whether your design will function correctly, as-is. If precise alignment is necessary, it must … Continued
Clock Domain Crossing (CDC)

Clock Domain Crossing (CDC) Made Simple: Best Practices for Vivado Users

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Managing clock domain crossing (CDC) is one of the most critical — and sometimes confusing — challenges in FPGA design. With modern designs often spanning multiple clock domains, ensuring safe data transfer across these domains is essential to avoiding metastability, timing issues, and unreliable system behavior. In this post, we’ll walk through how to approach … Continued

Achieving Timing Closure with Vivado Intelligent Design Runs

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Vivado Intelligent Design Runs (IDR) are a powerful feature that helps designers achieve timing closure more efficiently. Timing closure is often one of the most persistent and frustrating challenges in FPGA development. For complex designs, especially those targeting UltraScale and UltraScale+ devices, traditional trial-and-error tuning of implementation strategies can lead to long debug cycles and … Continued

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