Category: FPGA

Using QEMU with PetaLinux and Vitis for Embedded Software Development

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QEMU is a powerful emulation tool that enables early software debugging for complex SoCs like the AMD Zynq UltraScale+ MPSoC, without the need for physical hardware. When paired with PetaLinux and the AMD Vitis development environment, QEMU creates an efficient workflow for embedded Linux development and debugging. This post explains what these tools are, how … Continued

BLT Attends Microchip FPGA Tech Day: Diving Deep into FPGA Innovations

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Staying at the forefront of embedded systems and FPGA design requires more than just experience. It demands continuous learning and real-time engagement with the latest technologies. That’s why, at BLT, we make it a point to attend key industry events that give us access to the tools, techniques, and innovations shaping tomorrow’s solutions. This week, … Continued

Verilog vs VHDL: Choosing the Right HDL for FPGA Design

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The two dominant hardware description languages (HDLs), Verilog and VHDL, are both well-established, widely supported, and capable of describing complex digital systems. While each language can be used to create functionally identical hardware, they differ significantly in syntax, style, and design philosophy. When developing FPGA designs, selecting the right HDL is one of the first … Continued

Demystifying I/O Timing Constraints

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I/O timing constraints can be daunting, even for experienced FPGA designers. A common misconception is that these constraints somehow fix skewed input signals. They don’t. While synthesis and implementation tools can tolerate some signal misalignment, constraints are always required to determine whether your design will function correctly, as-is. If precise alignment is necessary, it must … Continued
Clock Domain Crossing (CDC)

Clock Domain Crossing (CDC) Made Simple: Best Practices for Vivado Users

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Managing clock domain crossing (CDC) is one of the most critical — and sometimes confusing — challenges in FPGA design. With modern designs often spanning multiple clock domains, ensuring safe data transfer across these domains is essential to avoiding metastability, timing issues, and unreliable system behavior. In this post, we’ll walk through how to approach … Continued

Achieving Timing Closure with Vivado Intelligent Design Runs

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Vivado Intelligent Design Runs (IDR) are a powerful feature that helps designers achieve timing closure more efficiently. Timing closure is often one of the most persistent and frustrating challenges in FPGA development. For complex designs, especially those targeting UltraScale and UltraScale+ devices, traditional trial-and-error tuning of implementation strategies can lead to long debug cycles and … Continued
RF Analyzer

Comprehensive Overview of the RF Analyzer in AMD Vivado

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The RF Analyzer in AMD Vivado represents a significant advancement in RF signal processing and analysis, tailored to address the complex requirements of modern communication systems, radar applications, and more. By bridging sophisticated configuration capabilities with user-friendly GUI controls, the tool equips engineers with the precision and flexibility required for optimal ADC (Analog-to-Digital Converter) and … Continued

AMD Versal AI Engine and AI Engine-ML. Which is right for you?

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The AMD Versal architecture introduced a new adaptable compute domain, the AI Engine. The AI Engine is a powerful coprocessor that can be used to implement vectorized algorithms that otherwise would be resource intensive on a traditional FPGA. While the amount of AI Engine tiles varies across the Versal lineup, the AI Engine itself is … Continued

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