FPGA Archives

Understanding Vivado Timing Reports: Analyzing Clocks and Timing in FPGA Designs

March 4, 2025

The AMD Vivado IDE (Integrated Development Environment) produces several Vivado timing reports that support analysis of the clocks implemented within an FPGA design. These are the Clock Networks Report and the Clock Interaction Report. It also has reports that assess the timing of a placed and routed design. These are the Timing Summary Report and … Continued

AMD Versal AI Engine Design Considerations: Harnessing the Power of the Versal AI Engine

February 18, 2025

By BLT Inc

The AMD Versal architecture introduced a brand new compute domain, the AI Engine. The Versal AI Engine is a powerful coprocessor that can be used to implement vectorized algorithms that wouldn’t otherwise be possible on an FPGA. The AI Engine’s architecture, a systolic array of SIMD VLIW coprocessors, represents a brand new architecture that is … Continued

Understanding the AXI Protocol: Applications and Functionality

February 6, 2025

By BLT Inc

The AXI protocol is powerful and easy-to-use for connecting modules within SoCs and FPGAs. Intro to the AXI Protocol AXI (Advanced eXtensible Interface) is an interface for connecting modules within an SoC or an FPGA. It is fully synchronous and can be as wide and as fast as needed to meet transfer requirements between modules. … Continued

Leveraging Vivado QoR Reports to Optimize FPGA Design Performance

January 22, 2025

By BLT Inc

Vivado QoR Reports are powerful tools in the Vivado Integrated Development Environment that help designers enhance the Quality of Results (QoR) for their FPGA designs. These include the DRC Report, the Methodology Report, the Design Analysis Report, the QoR Assessment Report, and the QoR Suggestions Report. The Vivado QoR Reports predict potential improvements that designers … Continued

Stop Having So Many States in Your Finite State Machines! – A Guide to Using FSMs

November 4, 2024

By BLT Inc

What starts as a simple task can quickly spiral into something far more complex—whether it's home repairs, birthday parties, or, unfortunately, Finite State Machines (FSMs). In Hardware Description Language (HDL), it’s easy to keep adding states—“wait” states, nested states, and so on. While these states are meant to simplify logic and improve maintainability, they often … Continued

Intel (Altera) FPGAs – A Brief History (And Comparison to AMD Xilinx FPGAs)

November 20, 2023

By BLT Inc

Throughout the last few decades in Programmable Logic Devices (PLD) the two most well-known FPGA suppliers were Altera and Xilinx. Altera is now part of Intel (PSG) and Xilinx was acquired by AMD. In an earlier post we discussed the logic resources of AMD Xilinx FPGAs and the Configurable Logic Block (CLB). This post will … Continued

The Configurable Logic Block – A Quick Look

November 9, 2023

By BLT Inc

In this post, we will quickly review the Configurable Logic Block (CLB) and how it has changed over the years. In 1984, Xilinx introduced the first FPGA to the world, the XC2064. This FPGA formed the backbone of later device families and the design flow leveraged the Xilinx XACT tool. Nearly 40 years later, FPGAs … Continued

Unlocking the Power of Cross Triggering on FPGAs

October 26, 2023

By BLT Inc

Understanding Cross Triggering (and why it's your friend) Cross triggering is a useful technique to help with debugging FPGAs. Field-Programmable Gate Arrays (FPGAs) are extremely versatile hardware platforms known for their ability to implement custom digital logic in the matter of seconds through the uploading of a bitstream. The applications of FPGAs range through many … Continued

What Is the AMD Xilinx UltraFast Design Methodology?

September 25, 2023

By BLT Inc

In FPGA (Field-Programmable Gate Array) development and design, speed, efficiency, and reliability are paramount. Engineers and developers are constantly seeking innovative methodologies to streamline the design process and deliver optimized solutions. AMD (formerly Xilinx), a prominent player in the FPGA industry, offers a cutting-edge approach known as the "UltraFast Design Methodology" to address these challenges. … Continued

Understanding What High-Level Synthesis (HLS) Is: Bridging the Gap Between Software and Hardware

August 21, 2023

By BLT Inc

In electronics and digital design with FPGAs and SoCs, the demand for more efficient, powerful, and faster hardware is unrelenting. Engineers and developers require ways to optimize their designs, making them faster and more energy efficient. One of the transformative technologies available to address this challenge is High-Level Synthesis (HLS). It plays a crucial role … Continued

Category: FPGA