BLT SAR AI Engine Implementation with Versal VCK190

BLT AI Engine Implementation for SAR on AMD Versal VCK190

Synthetic Aperture Radar (SAR) works by moving the Aperture (antenna) through space and compiling a result based on a compilation of the varying views of the data captured. As such, SAR processing involves demanding, high-throughput computations, especially when resolution, latency, and scalability are critical. To demonstrate what’s possible with the AMD Versal Adaptive SoC, AMD … Continued

Mastering Advanced Triggering with Trigger State Machines in ILAs

When debugging FPGA designs, simple triggers often don’t cut it. Complex designs frequently require capturing data only after a specific sequence of events or when multiple signals meet intricate conditions. This is where advanced triggering with trigger state machines (TSMs) comes into play, giving engineers powerful control over when and how data capture starts within … Continued

What Is PCIe?

What is PCIe? PCI Express (PCIe) is a high-speed serial interface used to connect processors and peripherals in everything from servers and workstations to embedded systems and FPGAs. If your system needs to move a lot of data fast, it is likely the protocol that makes it happen. PCI stands for Peripheral Component Interconnect in … Continued

Using QEMU with PetaLinux and Vitis for Embedded Software Development

QEMU is a powerful emulation tool that enables early software debugging for complex SoCs like the AMD Zynq UltraScale+ MPSoC, without the need for physical hardware. When paired with PetaLinux and the AMD Vitis development environment, QEMU creates an efficient workflow for embedded Linux development and debugging. This post explains what these tools are, how … Continued
Finite State Machines (FSMs)

Stop Having So Many States in Your Finite State Machines! – A Guide to Using FSMs

What starts as a simple task can quickly spiral into something far more complex—whether it's home repairs, birthday parties, or, unfortunately, Finite State Machines (FSMs). In Hardware Description Language (HDL), it’s easy to keep adding states—“wait” states, nested states, and so on. While these states are meant to simplify logic and improve maintainability, they often … Continued