The AMD Versal™ RF Series Adaptive SoCs mark a groundbreaking advancement in RF system design. They offer unprecedented capabilities for direct digital sampling and processing. AMD Versal RF Series Adaptive SoCs (FPGAs) provide direct digital sampling of wideband signals into the X and Ku bands. They offer massive compute capability within an array of Versal Adaptable Intelligent Engines (AIEs) coupled with hard IP blocks that perform common functions such as FFTs, Channelizers, and LDPC decoding. Applications processing is performed in a cluster of ARM cores and platform management components.
AMD Versal RF Series devices offer a size, weight, and power (SWaP) optimized single-chip solution to meet enhanced system design requirements. In total, AMD Versal RF Series devices enable high performance RF system implementations with significant reduction in system cost. Their capabilities make them a significant consideration for Electromagnetic Spectrum Operations (EMSO), Radar, MILCOM / SATCOM, Wideband Spectrum Analysis, and for Pre-6G Systems.
Applications and Solutions with the AMD Versal RF Series
AMD Versal RF Series Adaptive SoCs (FPGAs) extend the RF processing capability significantly beyond previous generations of RFSoCs to meet an expanded range of applications and solutions. The increased bandwidth supported by the ADCs and DACs expands the RF processing beyond applications like 5G radio. Also, the hard IP added in the Versal RF devices greatly simplifies channelized RF signal generation and reception.
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Enhanced Broad Spectrum Processing
Advances in RF spectrum usage require enhanced broad spectrum processing. The RF spectrum is becoming increasingly congested and contested in both commercial and mission critical applications. Advanced techniques are required to efficiently use the bandwidth available without compromising signals in adjacent bands. Similarly, tightly packed channels require specialized processing to receive and extract signals of interest.
Optimum Size, Weight, and Power
AMD Versal RF Series Adaptive SoC provide solutions with optimum size, weight, and power (SWaP). This means that the AMD Versal RF Series Adaptive SoCs are a heterogeneous integration at chip level of individual blocks each optimized for RF processing in the X and Ku bands. The RF data converter tiles are hard IP that tightly integrates the required blocks to directly sample RF signals and then down-convert the signals of interest for processing.
Similarly, the FFT/iFFT, Channelizer, and Polyphase Arbitrary Resampler are hard IP blocks optimized for applications like channelized signal processing and synthetic aperture radar. These hard IP blocks use the smallest amount of silicon die area possible to perform these functions. This results in the lowest possible area and lowest power consumption to perform these functions while leaving the AI Engines, DSP slices and Programmable Logic to perform enhanced and unique customer-defined processing. Lastly, the Processing System is also a hard IP block of APU and RPU cores and platform management components that supports extensive applications processing to control and further process the signals within the Versal RF device.
Functional Elements in the AMD Versal RF Series
AMD Versal RF Series Adaptive SoC feature all of the building blocks of previous generation Zynq™ UltraScale+™ RFSoCs with enhanced capabilities while adding additional capabilities to extend the range of supported applications. Each of these functional elements will be discussed in the following sections.
Enhanced ADCs and DACs
AMD Versal RF Series devices contain up to 16 RF-ADCs that sample at up to 32GSPS with an RF bandwidth of 18GHz. They also contain up to 16 RF-DACs that operate at up to 16GSPS with an RF bandwidth of 18GHz. This compares to 5.9GSPS for the ADCs and 10GSPS for the DACs with an RF bandwidth of 7.125GHz of the previous generation RFSoC devices. The ADCs each complement a Digital Down Converter (DDC) that contains a precision NCO, a complex mixer, and configurable decimation blocks. Similarly, the DACs each complement a Digital Up Converter (DUC) that contains a precision NCO, a complex mixer, and configurable interpolation blocks. These DDCs and DUCs are efficiently implemented in hard IP for minimum footprint and power savings.
Versal AI Engines
AMD Versal RF Series Adaptive SoC support all of the compute capability of prior generation RFSoCs while adding an array of AI Engines. They also include the enhanced DSP58 slices. These processing elements massively extend the digital signal processing capability of the device. Previous generations only supported generic digital signal processing using DSP48 slices.
AMD Versal RF Series Hard IP Accelerators
AMD Versal RF Series adaptive SoCs contain the following Hard IP Accelerators: FFT/iFFT, Channelizer, Polyphase Arbitrary Resampler, and enhanced LDPC Decoder blocks. Prior RFSoC devices contained simpler SD-FEC encoder/decoder blocks. These Hard IP Accelerators implement common processing functions with a minimum footprint. The Versal AIEs and DSP58 slices, therefore, can be best used to implement the customer’s application-specific processing. The Hard IP implements these highly used functions with up to 80% reduction in size weight and power.
The FFT/iFFT hard block enables fast spectrum analysis. It can process input signals at up to 4GSPS. It is configurable from 8-pt to 4K-pt. Larger FFTs can be supported by combining and cascading multiple hard IP blocks.
The Channelizer hard IP block can implement a polyphase filter bank channelizer which separates a wideband input spectrum into narrow subchannels. Multiple channelizer hard IP instances can be cascaded for additional resolution and accuracy.
The Polyphase Arbitrary Resampler hard IP block is provided for test & measurement applications. It can also perform general filtering. And, best of all, the user can select exactly the Hard IP desired in a multitude of configurations.
The enhanced LDPC decoder blocks support an updated version of SD-FEC decoding as well as DVB-S2/S2X satellite codes supporting space applications.
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Processing System
AMD Versal RF Series Adaptive SoCs contains a dual-core Arm Cortex-A72 application processor and a dual-core Arm Cortex-R5F real-time processor. They can be programmed to execute system applications that control and manage system operations. These compare with a quad-core A53 application processor and a dual-core Arm Cortex-R5 real-time processor contained in previous generation RFSoC devices. In all cases, the scaler processing cores complement the platform management and security blocks.
Programmable Logic
Both the AMD Versal RF Series Adaptive SoCs as well as previous generation RFSoCs implement a significant amount of programmable logic. The programmable logic can be used to implement any complex algorithm required for the application. It also supports Super Sample Rate (SSR) processing for RF data samples.
AMD Versal RF Series Connectivity
High throughput SERDES connectivity is available in all RF devices. The AMD Versal RF Series adaptive SoCs support GTM transceivers that support up to 112G PAM4 links. Prior generation RFSoC devices supported only 33G links.
Summary
AMD Versal RF Series Adaptive SoCs are highly integrated RF signal processing devices. They support a wide range of applications into the X and Ku bands. They also contain many hard IP accelerators that provide commonly used functions in a minimum amount of silicon die space. This results in optimally reduced size, weight and power. The AMD Versal RF Series Adaptive SoC offer significantly more bandwidth and processing capability over previous generation RFSoC devices.