The AMD Vivado IDE (Integrated Development Environment) produces several Vivado timing reports that support analysis of the clocks implemented within an FPGA design. These are the Clock Networks Report and the Clock Interaction Report. It also has reports that assess the timing of a placed and routed design. These are the Timing Summary Report and the Datasheet Report.
Vivado Timing Reports: Clock Networks Report
The Clock Networks Report is used to generate a tree view of the clock networks in the design so that the designer can visualize the propagation of clocks through the design. Each clock tree will show the clock network from source to endpoint with the endpoints sorted by type. The Clock Networks Report provides all the clocks in the design, including constrained and unconstrained clocks and primary and generated clocks. It also shows the network fanout of each clock net from I/O port to load, which BUFG is driving other BUFGs, and which clocks are driving non-clock loads. Note that the full clock tree is only detailed in the GUI form of the report. The text version of this report just shows the name of the clock roots.
The Clock Networks Report can only be initiated when either a synthesized design or an implemented design is opened within the Vivado IDE.
Then, generate the report by either:
- Selecting Report Clock Networks in the Flow Navigator under either Network Analysis -> Open Synthesized Design or under Implementation -> Open Implemented Design,
- Issuing the TCL command ‘report_clock_networks -name {network_1}’ to get the GUI form of the report, or
- Using the menu selections Reports -> Timing -> Report Clock Networks.
Vivado Timing Reports: Clock Interaction Report
The Clock Interaction Report shows the clock interactions and signals that cross from one clock domain to another. The report helps identify problems such as metastability, data loss, and incoherency.
The Clock Interaction Report uses an inter-clock path matrix to show the clock relationships and group paths. It displays this matrix as a grid. The report is used as a sanity check to show the need for synchronization circuitry and to verify that timing constraints have been added to cover paths between unrelated clock domains.
Each box in the grid shows the relationship between a source clock and a destination clock. The boxes are colored to match the constraints that exist between the clocks.
Indicators:
- Black squares indicate that there are no paths between the two clocks (i.e. no paths from a flip-flop on the source clock to a flip-flop on the destination clock).
- Green squares confirm that paths between the two clock domains are properly constrained.
- Dark blue squares indicate user ignored paths that have set_false_path assigned to all paths between these clock domains.
- Red squares indicate unsafe clock domain crossings that have no harmonic relation (i.e. are asynchronous) and have no exceptions.
- Light blue squares indicate partial false path. Some paths have exceptions and others do not.
- Gray squares indicate that all domain crossings only have a max delay datapath exception (i.e. set_max_delay -datapath_only).
- Orange squares are nearly as unsafe as red ones. Some paths have no exceptions and the clocks are asynchronous.
There is also a table below the color-coded grid that lists the number of paths for each square. Exceptions can be easily applied by right-clicking on any of these rows and then applying them to the selected clock domains crossings.
The Clock Interaction Report can only be initiated when either a synthesized design or an implemented design is opened within the Vivado IDE.
Then, generate the report by either:
- Selecting Report Clock Interaction in the Flow Navigator under either Network Analysis -> Open Synthesized Design or under Implementation -> Open Implemented Design,
- Issuing the TCL command ‘report_clock_interaction -name clocks_1’ to get the GUI report output, or
- Using the menu selections Reports -> Timing -> Report Timing Summary.
Vivado Timing Reports: Timing Summary Report
Timing analysis is available anywhere in the flow after synthesis, and the Timing Summary Report is automatically created by the synthesis and implementation runs. In a synthesized design, the Vivado timing engine estimates the net delays based on connectivity and fanout, whereas in an implemented design, the net delays are based on the actual routing information. Therefore, it reports the worst-case timing analysis.
The Timing Summary Report is a single report that provides a complete “sign-off” on the timing of your design. It has several sections for complete timing reporting.
Timing Summary Report – First Section
First is the General Information section, which displays the design name, the target device, package, and speed grade, the Vivado IDE version, the execution date, and the equivalent TCL command executed.
Timing Summary Report – Second Section
The second section, Timer Settings, provides information on the Vivado timing analysis engine settings used to generate the timing information. This includes enabling or disabling multi-corner analysis, pessimism removal, preset / clear arcs, and flight delays.
Timing Summary Report – Third Section
The third section is the most important. It provides a summary of the timing for the design and combines the results of all the other sections into one view. This section helps you determine whether the design has met the timing requirements or not. The Design Timing Summary section includes the setup, or max delay analysis; hold, or min delay analysis; and the pulse width, or pin switching limits. The setup, or max delay analysis, calculates worst negative slack and total negative slack, or WNS and TNS, and failing endpoints. The hold, or min delay analysis, calculates worst hold slack and total hold slack, or WHS and THS, and failing endpoints. The pulse width analysis calculates max or min pulse width and the period.
Timing Summary Report – Fourth Section
The fourth section is the Clock Summary section, which has information on all the clocks in the design. It then lists the properties for each clock, such as name, period, waveform, and target frequency. The fifth section, Check Timing, contains information about missing timing constraints or paths with constraint issues that need review. For complete timing signoff, all path endpoints must be constrained. The check timing routine runs a series of default timing checks and reports a summary of any violations found. The lists the missing information about generated clocks, loops, multiple clocks, and unconstrained endpoints. It finds whether there are any clock or I/O constraints that are missing. It also reports whether any input or output has partially defined constraints.
Timing Summary Report – Fifth and Sixth Sections
The next two sections are the Intra-Clock path section and the Inter-Clock path section. The Intra-Clock path section summarizes the worst slack and total violations of timing paths with the same source and destination clock. The Inter-Clock path section summarizes the worst slack and total violations of the timing paths between different source and destination clocks.
Timing Summary Report – Last 3 Sections
The last three sections list exceptions of various types. They are the Other Path Groups Section, the User Ignored Paths Section, and the Unconstrained Paths Section. The Other Path Groups section displays default path groups and user-defined path groups. The User Ignored Paths section displays the ignored paths during the timing analysis due to the set clock groups and set false path timing exception constraints. The Unconstrained Path section displays the logical paths that are not timed due to missing timing constraints. These paths are grouped by source and destination clock pairs.
The Timing Summary Report can only be initiated when either a synthesized design or an implemented design is opened within the Vivado IDE.
Then the report can be generated either by:
- Selecting Report Timing Summary in the Flow Navigator under either Network Analysis -> Open Synthesized Design or under Implementation -> Open Implemented Design,
- Issuing the TCL command ‘report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1’ to get the standard report output, or
- Using the menu selections Reports -> Timing -> Report Timing Summary.
Vivado Timing Reports: Datasheet Report
The Datasheet Report generates a list of timing parameters for your FPGA implementation similar to the timing report you would find for any electronic device. It is based on the constraints applied to the design. The datasheet report gives you information about the operating parameters of the FPGA device for use in system-level integration. It also tells you the requirements of the interface after the implementation stage.
The Datasheet Report has the following sections:
- Datasheet Report Summary which lists the design name, the selected FPGA part, package and speed grade, Vivado IDE version, the report execution date and the command issued to obtain the report,
- Setup and hold time of input ports in respect to their associated clock,
- Propagation delays to output ports in respect to their associated clock,
- Setup margin between timed clock domains,
- Setup and hold time of input buses in respect to their associated clock, and
- Propagation delays to output buses in respect to their associated clock.
The Datasheet Report can only be initiated when either a synthesized design or an implemented design is opened within the Vivado IDE.
Then, generate the report by either:
- Issuing the TCL command ‘report_datasheet -name timing_1’ to get the GUI report output, or
- Using the menu selections Reports -> Timing -> Report Timing Summary.
Vivado Reports: QoR Report
View our blog post about QoR here.
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Conclusion
In summary, Vivado timing reports provide essential insights into the clocking and timing performance of FPGA designs. The Clock Networks Report helps visualize clock propagation, while the Clock Interaction Report identifies potential issues in clock domain crossings. The Timing Summary Report serves as a comprehensive timing sign-off, and the Datasheet Report provides critical timing parameters for system-level integration. By leveraging these reports, designers can analyze, debug, and optimize their FPGA implementations to achieve reliable and efficient performance.
