Vivado QoR Reports are powerful tools in the Vivado Integrated Development Environment that help designers enhance the Quality of Results (QoR) for their FPGA designs. These include the DRC Report, the Methodology Report, the Design Analysis Report, the QoR Assessment Report, and the QoR Suggestions Report.
The Vivado QoR Reports predict potential improvements that designers can implement early in the design cycle. By using these reports, designers increase the likelihood that their designs will route successfully, meet timing constraints, and function as intended. Designers can improve a design’s QoR either by modifying the design itself or by adjusting the constraints.
DRC Report
The Design Rule Check (DRC) Report checks the design against a specified set of design rules and identifies any errors or violations. Designers can enable or disable thousands of design rules selectively based on specific requirements and the current development stage.
When designers select the DRC report in the IDE, a window opens to let them choose or deselect design rules organized hierarchically. After selecting the relevant rules, the generated report lists violations grouped by type, allowing designers to focus on the most critical issues. The DRC Report assigns violations one of three severity levels:
- Info: Indicates informational issues that require review but may not impact functionality.
- Warning: Highlights potential problems that warrant attention, even if functionality remains intact.
- Critical: Identifies issues that must be resolved before moving forward.
Designers can generate the DRC Report when a synthesized or implemented design is open in the Vivado IDE. They can do this by:
- Selecting Report DRC in the Flow Navigator under Network Analysis → Open Synthesized Design or Implementation → Open Implemented Design.
- Entering the TCL command
report_drc -name drc_2 -ruledecks {default}for the GUI version of the report. - Using the IDE menu and navigating to Reports → Report DRC.
Methodology Report
The Methodology Report applies design rule checks based on the UltraFast™ Design Methodology, a set of best practices that optimize designs for success. Designers should run this report at each design stage to validate the following:
- RTL constructs before synthesis.
- The netlist and constraints after synthesis.
- Constraints and timing-related elements after implementation.
The Methodology Report categorizes rule violations into three levels of severity:
- Advisory: Offers general feedback on design processing.
- Warning: Points out suboptimal results caused by constraints or specifications that may not align with intentions.
- Critical Warning: Highlights significant issues requiring immediate changes to ensure best practices are followed.
For instance, if the design does not contain delay constraints for an input or output pin, this will be flagged with a warning.
The Methodology Report can only be initiated when either a synthesized design or an implemented design is opened within the Vivado IDE. Then the report can be generated either by:
- Selecting Report Methodology in the Flow Navigator under Network Analysis → Open Synthesized Design or Implementation → Open Implemented Design.
- Using the TCL command
report_methodology -name ultrafast_methodology_2. - Navigating to Reports → Report Methodology in the IDE menu.
Design Analysis Report
To quickly assess QoR, designers can run the Design Analysis Report with the -qor_summary option after synthesis. This report provides insights into timing path characteristics, interconnect complexity, and congestion, enabling designers to make informed decisions to optimize QoR. Designers can generate the report by entering the TCL command report_design_analysis -qor_summary while a synthesized or implemented design is open.
Vivado QoR Assessment Report
The QoR Assessment Report estimates the likelihood that a design will meet timing goals. This text-based report provides designers with an early indication of whether their design will achieve performance targets.
The QoR Assessment Report includes:
- An assessment score that indicates how likely the design is to meet performance targets,
- Flow guidance on the recommended next steps,
- A summary of utilization and performance metrics,
- A summary on methodology checks critical to QoR, and
- Information on the availability of machine learning strategies to meet timing (only available on routed designs).
This report analyzes multiple performance metrics and provides a design score in the range of 1–5, where:
- 1 stands for “Design is unlikely to complete the implementation flow”,
- 2 stands for “Design will complete the implementation flow but is very unlikely to meet timing constraints”,
- 3 stands for “Design is unlikely to meet timing constraints”,
- 4 stands for “Design may meet timing”, and finally
- 5 stands for “Design will easily meet the timing”.
Designers can generate this report by entering the TCL command report_qor_assessment. It helps them decide whether to continue implementation, adjust the netlist or constraints, or alter performance targets. Before requesting this report, designers should resolve DRC and Methodology violations.
Vivado QoR Suggestions Report
The QoR Suggestions Report analyzes the design and returns a list of possible improvements to enhance the QoR. Plus, the report looks at timing constraints, netlist characteristics, failing timing paths, and congestion information to determine the suggestions that can enhance the QoR. Suggestions are grouped under the headings: XDC, Timing, Utilization, and Clocking.
The QoR Suggestions Report also supports a scorecard reporting method. It can be used in conjunction with three other TCL commands to enable this feature. They are:
write_qor_suggestions: Saves suggestion objects to a file.read_qor_suggestions: Reads suggestion objects from a file.get_qor_suggestions: Returns QoR suggestion objects as a query.
When designers generate a QoR Suggestions Report, it includes updates on resolved suggestions and lists new recommendations. They can create this report by entering the TCL command report_qor_suggestions or by selecting Reports → Report QoR Suggestion/Assessment in the IDE menu.
Conclusion
Vivado QoR Reports provide FPGA designers with invaluable insights and tools to optimize their designs at every stage of the development process. From ensuring compliance with design rules using the DRC Report to adopting best practices with the Methodology Report, these reports empower designers to identify and address potential issues early. The Design Analysis, QoR Assessment, and QoR Suggestions Reports further enhance this process by offering actionable feedback and improvement strategies tailored to the design’s specific challenges.
By leveraging these comprehensive reporting features, designers can not only improve the Quality of Results (QoR) but also increase efficiency, reduce design iterations, and achieve higher confidence in meeting project goals. Incorporating Vivado QoR Reports into your workflow is a smart and strategic approach to FPGA design success.
