Unlocking the Power of Cross Triggering on FPGAs

Understanding Cross Triggering (and why it’s your friend)

Cross triggering is a useful technique to help with debugging FPGAs. Field-Programmable Gate Arrays (FPGAs) are extremely versatile hardware platforms known for their ability to implement custom digital logic in the matter of seconds through the uploading of a bitstream. The applications of FPGAs range through many different fields including telecommunications, aerospace, data processing, and especially embedded systems. FPGAs and their applications can be very involved and sometimes require complex debugging when things don’t go as planned. In this situation, a method known as cross triggering can come into play. It allows a designer to gather information from the FPGA logic during operation with custom criteria. Let’s delve into the concept of cross triggering with FPGAs, what it is, how it works, and its many applications.

What is Cross Triggering?

In FPGAs, there is a module that is often implemented when debugging a design on the bench. This is called an ILA in Vivado (AMD Xilinx) or a Signal Tap in Quartus (Intel). (For efficiency, we’ll just refer to this module as an ILA in this blog post.) The goal of this module is to capture different logical signals that are defined by the designer, so that they can see how and what data is being processed in their design. Once they have this information, they can compare it against what they were expecting, typically determined through simulation.

Due to the clock speeds within FPGAs, it can be difficult to capture the correct data when debugging. This is where triggering comes into play. An ILA can be triggered by many things, including one – or many – signals being equal to specific values simultaneously, a signal transitioning from one value to another, or through cross triggering.

Cross triggering allows synchronization between multiple ILAs or between an ILA and a processor inside of the FPGA. This allows the designer to see the logical state of multiple sections of the FPGA all at the same time. Cross triggering really begins to shine with embedded systems. Processors being non-deterministic and digital logic being deterministic in nature with regards to their cycles per operation is why. Frequently, the only point of contact between a design in the FPGA fabric and a processor is a couple data buses, whether the processor be bare metal, soft-core, or a full processing system.

How Does Cross Triggering Work?

Cross triggering utilizes special trigger signals that are asserted by other ILAs when they are triggered or by a processor when it reaches a breakpoint. Cross triggering also extends to creating a breakpoint in the software when an ILA in the hardware triggers. This allows the designer a unique view into the processor that is often not achievable otherwise.

Trigger Propagation

It is also possible to chain multiple ILAs together in a daisy chain configuration. This allows a single ILA or processor to either send a trigger signal that it receives or a trigger signal that it asserts itself to any debug modules downstream from it.


Applications of Cross Triggering on FPGAs

While cross triggering can be applied to most large FPGA designs, these are some examples of applications that are able to best use cases:

Real-time Control Systems

In many real-time applications, the design must generate a response within a tightly constrained amount of time, in some applications even down the nanosecond. Unexpected delays in a design may cause it to fail the timing requirements. Cross triggering can allow one module in the FPGA to trigger an ILA in another region. This technique lets the designer evaluate the state of the logic and will help them locate the area of concern.

Data Processing Pipelines and Digital Signal Processing (DSP)

In any data processing application, whether data-center-based or RF-based, it will require a significant number of mathematical operations to perform its task. The designs that implement these math pipelines often use pipelining stages to achieve a higher clock rate. This allows that part of the design to run faster.

Unfortunately, a missed pipeline stage or a misjudged data alignment can occur and the only information that the designer has is the incorrect output. Cross triggering can allow a start signal to any of these data pipelines to capture the data inputs in one ILA and then capture data farther down the line in the pipeline after some number of calculations are done with another ILA. This gives the designer insight into different stages of the operations. Plus, it allows them to determine when the math operations are going awry.

Cross triggering is a powerful application because, in many of these use cases, a software application initiates the data processing. Cross triggering enables an ILA to capture digital logic inputs at the beginning of a process initiated by software to validate that the data inputs are arriving on time.

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Benefits of Cross Triggering


Cross triggering ensures that data across multiple areas of the FPGA fabric and processors can be captured by ILAs and breakpoints simultaneously. Without cross triggering, the FPGA designer would have to finely tune many different configurations. Configurations include getting the software and hardware to capture relevant data sets. However, there is no true guarantee that the data is aligned correctly or not.

Resource Efficiency

Even though ILAs are meant to be temporary design modules, they add resources and consume space on any FPGA. The reason is that often the routing resources are required to supply the ILA with the proper trigger signals. This can lead to complications in the debugging process, such as struggling to create a build that meets timing with the ILA instantiated, especially with a large design. Cross triggering can allow multiple ILAs to trigger from a single cross-trigger signal supplied by an upstream ILA. This means that the digital logic signals can route to a single ILA, instead of 5 ILAs, for example. This can cut down on the resource utilization drastically. It will always be easier to route a single wire than four 32-bit values to 5 separate places.

Challenges and Considerations with Cross Triggering

Although cross triggering is becoming increasingly more useful as designs continue to grow more complex, the complexities of implementing ILAs and their cross triggering features become more complex as well.


Designs are becoming larger and more regions of an FPGA are included in the debugging process. This means the control sets will continue to grow as well. These control sets are often the signals used in the trigger conditions for ILAs. They then go on to generate a cross trigger signal. An ILA’s trigger conditions in a complex design will often include multiple different cases across the same control set, or even a small state machine. This can lead to debugging the settings for your ILA instead of being able to debug your design.


ILAs can provide useful insight into what is occurring in an FPGA build. But there is no guarantee that it will provide conclusive results as to the true problem. The data captured from an ILA and cross triggering will often point the engineer to the area of the problem. Analyze this data using schematics, block designs, and simulations to determine the true cause of the bug.


Cross triggering is a powerful feature in any FPGA design when on the bench. It can allow the engineer to coordinate multiple different areas of the FPGA including a processor to get a snapshot of their design and its state at a specific time during operation. Its applications can truly be boiled down to any FPGA design with multiple areas operating independently. While incredibly useful, use only as a worst-case scenario. It’s usually quicker to simulate a bug than to implement an ILA and rebuild the project over several iterations to determine the issue. With that said, it is important that when simulation shows there are no issues, the designer is aware of, and can utilize, cross triggering to speed up their time on the bench!

Cross Triggering