Using OpenCL Framework for FPGAs

Developing and Optimizing Applications Using the OpenCL Framework for FPGAs

DEPRECATED COURSE: This course is older and no longer offered with our regular course list. It is only available as a private class.

Please contact the BLT Training Team to schedule a private class.

Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel development environment for use on AMD Xilinx FPGAs. Porting existing applications is also covered.

This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources.

See Course Outline

Training Duration:

2 Days

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Who should attend:

Software and hardware developers who want to develop OpenCL, C/C++, and RTL applications in the SDAccel development environment.

Skills Gained

After completing this comprehensive training, you will know how to:

Identify parallel computing applications suitable for accelerating on FPGAs
Discover how the FPGA architecture lends itself to parallel computing
Write OpenCL programs for FPGAs
Examine the OpenCL execution model
Analyze the OpenCL memory model
Profile and debug OpenCL code using the SDAccel development environment
Discover how to maximize performance in FPGA fabric
Efficiently utilize FPGA memory resources
Utilize the SDAccel development environment
Rapidly develop FPGA applications using OpenCL
Port programs written in OpenCL for CPUs or GPUs to Xilinx FPGAs

Course Outline

Day 1	Day 2
Introduction to OpenCL Comparison of CPU, GPU, and FPGA Architectures OpenCL Support for Xilinx FPGAs FPGA Hardware Details Introduction to the OpenCL API LAB: Creating an OpenCL Program from Scratch Creating an OpenCL Program from Scratch Provides an overview of OpenCL API, memory transfers, and kernel enqueuer operations. OpenCL Execution Model LAB: Vector Addition Vector Addition Learn how to execute parallel kernels. Memory Hierarchy Profiling and Debugging LAB: Pi by Monte Carlo Processes Pi by Monte Carlo Processes Implement the Pi by Monte Carlo processes. Optimization LAB: Maximizing Performance Maximizing Performance Use vector data types and increase bandwidth. LAB: Optimizing Kernels Optimizing Kernels Use Loop Unrolling and Loop Pipelining.	Using the SDAccel Development Environment: Coding, Compiling, Emulating, Profiling, and Debugging LAB: Profiling and Debugging Using the SDAccel Development Environment GUI Profiling and Debugging Using the SDAccel Development Environment GUI Learn how to use interactive programming tools to improve performance and squash bugs. Using Existing C/C++ Code as Kernels in OpenCL LAB: Optimizing C/C++ Code for OpenCL Optimizing C/C++ Code for OpenCL Convert existing C/C++ code into a kernel that can be used by OpenCL RTL IP as Kernels in OpenCL LAB: Using an RTL Kernel Using an RTL Kernel Learn how to use existing, highly optimized IP in a new OpenCL application.

Day 1

Day 2

Introduction to OpenCL
Comparison of CPU, GPU, and FPGA Architectures
OpenCL Support for Xilinx FPGAs
FPGA Hardware Details
Introduction to the OpenCL API
LAB: Creating an OpenCL Program from Scratch
Creating an OpenCL Program from Scratch Provides an overview of OpenCL API, memory transfers, and kernel enqueuer operations.
OpenCL Execution Model
LAB: Vector Addition
Vector Addition Learn how to execute parallel kernels.
Memory Hierarchy
Profiling and Debugging
LAB: Pi by Monte Carlo Processes
Pi by Monte Carlo Processes Implement the Pi by Monte Carlo processes.
Optimization
LAB: Maximizing Performance
Maximizing Performance Use vector data types and increase bandwidth.
LAB: Optimizing Kernels
Optimizing Kernels Use Loop Unrolling and Loop Pipelining.

Using the SDAccel Development Environment: Coding, Compiling, Emulating, Profiling, and Debugging
LAB: Profiling and Debugging Using the SDAccel Development Environment GUI
Profiling and Debugging Using the SDAccel Development Environment GUI Learn how to use interactive programming tools to improve performance and squash bugs.
Using Existing C/C++ Code as Kernels in OpenCL
LAB: Optimizing C/C++ Code for OpenCL
Optimizing C/C++ Code for OpenCL Convert existing C/C++ code into a kernel that can be used by OpenCL
RTL IP as Kernels in OpenCL
LAB: Using an RTL Kernel
Using an RTL Kernel Learn how to use existing, highly optimized IP in a new OpenCL application.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of C/C++

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Updated 12-18-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.