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FPGA Design Best Practices

#1 Project Planning	While not a fatal error, failing to plan can often add costly weeks to identify then resolve challenges. "Most people don't plan to fail, they fail to plan." At BLT, planning is the first step of designing. When planned properly, an FPGAs design becomes easier not harder as one moves through the process. As the Navy saying goes: *"Plan the Dive then Dive the plan."* BLT designs FPGAs from this proven approach. Experience teaches us that engineers "pay now or pay later" and paying later is almost always more "expensive" than an up-front investment. Facets of creating FPGA solutions that can be hurt by a lack of planning include: The ability to quickly understand timing issues The ability to achieve timing closure The ability to issue timing constraints Comprehensive simulation and verification SSO (Simultaneously Switching Outputs) issues I/O standards issues Clocking and synchronous Design challenges Floorplanning Design for AT(Anti-Tamper) Designs using SCC/IDF (Isolated Design Flow) Overall design clarity and maintainability ul> With success and schedules in the balance, can you afford not to invest in planning? Contact BLT and ask how we can help you plan your next project.
#2 Synchronous Design	Given current and common FPGA devices and implementation and simulation tools, for most, failing to do to synchronous design is a recipe for disaster. BLT defines a synchronous circuit as one where all Flip Flops use using the same clock signal. (For proper operation, the clock signal must be skew limited.) Complicating the situation, modern FPGAs designs often contain multiple clock domains so properly managing domain crossings is critical.
#3 Simulation	We've seen many Client designs that work on the bench yet fail in simulation or once in the field. Don't get caught in this quality or schedule trap. Design with the rigor of an ASIC while retaining the ability to implement changes near-real-time. Can you trust the results you see on the bench? NO! Parts on the bench are guaranteed to be faster than worst case specifications. Your design may operate differently at different temperatures or with different parts. Does simulation take time? Yes. But it's still 10 times faster than debugging on the bench. A key to predictable and timely success with FPGAs is a commitment and belief in simulation. When BLT takes a design to the bench for verification, we've already seen it work in functional simulation and we've verified that it meets all static timing constraints.
#4 Structure	In short, Structure = Hierarchy and Hierarchy = The ability simulate bottom up and a logical, predictable, and reliable manor. The ability to target timing constraints in a leveraged and focused manor The ability to control placement on silicon Precise control of critical design elements Utilization of Partial Reconfiguration Access to the IDF/SCC flows (Isolated design flow / Sing Chip Crypto)
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