Reducing Simulation Time and Testbench Headaches: Using SystemVerilog with VHDL and Verilog Webinar
BLT, an AMD Platinum Embedded Design Services Partner and Authorized Training Provider, presents this webinar.
Think your testbench has to use the same HDL as your design? It doesn’t. In this webinar, you’ll learn how SystemVerilog can be used to build faster, more effective testbenches even when your FPGA design is written in VHDL or Verilog. We’ll explore how Bus Functional Models (BFMs) can simplify testbench development and how AMD simulation tools support mixed-language testbenches when designing for AMD devices, including Versal adaptive SoCs. See how you can use SystemVerilog’s powerful verification capabilities to save time and effort without rewriting your existing HDL. This webinar includes a live demo and Q&A.
If you are unable to attend, a recording will be sent one week after the live event.
