Zynq® Ultrascale+ MPSoC for the Hardware Designer

This one-day course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq® Ultrascale+ MPSoC family from a hardware architectural perspective.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • List the various power domains and how they are controlled
  • Describe the connectivity between the processing system (PS) and programmable logic (PL)
  • Utilize QEMU to emulate hardware behavior

Course Outline

Day 1

  • Zynq® Ultrascale+ MPSoC Application Processing Unit
    Introduction to the members of the APU, specifically the Cortex®�-A53 processor and how the cluster is configured and managed.
  • Zynq® Ultrascale+ MPSoC HW-SW Virtualization
    Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
  • Zynq® Ultrascale+ MPSoC Real-Time Processing Unit
    Introduction to the various elements within the RPU and different modes of configuration.
  • QEMU
    Introduction to the Quick Emulator, which is the tool used to run software for the Zynq® Ultrascale+ MPSoC device when hardware is not available.
  • Zynq® Ultrascale+ MPSoC Booting
    How to implement the embedded system, including the boot process and boot image creation.
  • Zynq® Ultrascale+ MPSoC System Protection
    Covers all the hardware elements that support the separation of software domains.
  • Zynq® Ultrascale+ MPSoC Clocks and Resets
    Overview of clocking and reset, focusing more on capabilities than specific implementations.
  • AXI
    Understanding how the PS and PL connect enables designers to create more efficient systems.
  • Zynq® Ultrascale+ MPSoC PMU
    Overview of the PMU and the power-saving features of the device.

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
Standard Registration
8 Training Credits
Advanced Registration
Advanced Registration
7 Training Credits
Basic Follow-on Coaching
Comprehensive Follow-on Coaching
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

1 Day

Who should attend:

Hardware designers interested in understanding the architecture and capabilities of the Zynq® Ultrascale+ MPSoC device.


Suggested: Understanding of the Zynq®-7000 architecture

Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Software Tools

Vivado Design Suite 2017.1May require special Zynq® Ultrascale+ MPSoC family licenseHardware emulation environment:VirtualBoxQEMUUbuntu desktopPetaLinux



Last Updated: 2019-06-06_1626