Ultrascale and Ultrascale+ Architectures Workshop

This is a one-day version of the Designing with the Ultrascale Architecture course and introduces new and experienced designers to the most sophisticated aspects of the Ultrascale and Ultrascale+ architectures. Targeted towards designers who have used the Vivado Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family.

Topics covered include an introduction to the clock management resources (MMCM and PLL), global and regional clocking resources, memory resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the Ultrascale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Take advantage of the primary Ultrascale architecture resources
  • Define the block RAM and FIFO resources available for Ultrascale FPGAs
  • Describe the UltraRAM features
  • Properly design for the I/O and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included with the Ultrascale architecture
  • Identify the hard IP resources available for implementing high-performance DDR4 physical layer interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the Ultrascale architecture as quickly as possible

Course Outline

Day 1

  • Ultrascale Architecture Clocking Resources
    Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.
  • FPGA Design Migration
    Migrate an existing 7 series design to the Ultrascale architecture.
  • Ultrascale Architecture Block Memory Resources
    Review the block RAM resources in the Ultrascale architecture.
  • Ultrascale Architecture FIFO Memory Resources
    Review the FIFO resources in the Ultrascale architecture.
  • UltraRAM Memory
    Use UltraRAM for a design requiring a larger memory size than block RAM.
  • DDR4 Design Creation Using MIG
    Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility.
  • Ultrascale Architecture I/O Resources Overview
    Provides an overview of the I/O resources in the Ultrascale architecture.
  • Ultrascale Architecture I/O Resources Component Mode
    Implement a high-performance, source-synchronous interface using I/O resources in Component mode for the Ultrascale architecture.
  • Ultrascale Architecture I/O Resources Native Mode
    Implement a high-performance, source-synchronous interface using I/O resources in Native mode for the Ultrascale architecture.
  • Ultrascale Architecture Transceivers
    Review the enhanced features of the transceivers in the Ultrascale architecture.
  • Ultrascale FPGAs Transceivers Wizard
    Use the Transceivers Wizard to build a design that uses a single serial transceiver and observe the created file structures.

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
$800
Standard Registration
8 Training Credits
Advanced Registration
$700
Advanced Registration
7 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$700
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

1 Day

Who should attend:

Anyone who would like to build a design for the Ultrascale or Ultrascale+ device family

Prerequisites

Designing FPGAs Using the Vivado Design Suite 1 course

Intermediate VHDL or Verilog knowledge

Software Tools

Vivado Design or System Edition 2017.1

Hardware

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Last Updated: 2019-06-06_1626