Designing with the Versal Adaptive SoC: Hardware Debug

COURSE CODE: ACAP-DEBUG

This course describes the tools and techniques available to debug AMD Versal devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers ChipScoPy APIs, which provide a Python interface to program and debug the Versal devices.

The emphasis of this course is on:

Describing the Versal device design flows
Enumerating the Versal device debug features for programmable logic (PL) and hard block debugging
Debugging the Versal device using different debug IP cores
Using ChipScoPy APIs for hardware debugging
Improving Versal device system performance

See Course Outline

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$600	6
In-Person Registration - $600/day	$600	6
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee)	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

1 Day

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

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Who should attend:

Hardware developers and system architects and anyone who wants to learn about the tools and techniques available
to debug the Versal device.

Software Tools

Vivado Design Suite 2024.1
Vitis Unified IDE 2024.1

Hardware

Architecture: Versal adaptive SoC
Demo board: Versal VCK190 Evaluation Platform

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe the different tool flows for AMD Versal devices
Identify the debug interfaces in the Versal devices
Utilize different debug IP cores, such as the AXIS ILA and AXIS VIO cores
Identify the different hard block debugging tools
Describe the Versal device debugging techniques for JTAG lowspeed debug and high-speed debug port (HSDP) debug
Utilize ChipScoPy APIs for hardware debugging

Course Outline

Day 1
Design Tool Flow Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab} Configuration and Debugging Describes the configuration and debug process for the Versal devices. Also covers the Versal device debug interfaces, such as the test access port (TAP) and debug access port (DAP) controller. {Lecture} Fabric Debug Explains the fabric debug features available in the Versal device and reviews the different debug IP cores supported for Versal devices, such as the AXI Debug Hub, AXIS ILA, and AXIS VIO. {Lecture, Lab} Hard Block Debug Focuses on the debugging of Versal device hard blocks, such as the GTs, NoC, DDRMC, HBM, PCIe block, PS, and AI Engines. {Lecture} Overview of HSDP Describes the high-speed debug port (HSDP) in the Versal device. Also goes over the steps to use the SmartLynq+ module for high-speed debugging. {Lecture, Lab} ChipScoPy Overview Discusses the ChipScope hardware debug method and reviews how the ChipScoPy APIs are used for debugging the Versal device. {Lecture} System Integration and Validation Methodology Describes different simulation flows as well as timing and power closure techniques. Also explains how to improve system performance. {Lecture}

Day 1

Design Tool Flow
Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}

Configuration and Debugging
Describes the configuration and debug process for the Versal devices. Also covers the Versal device debug interfaces, such as the test access port (TAP) and debug access port (DAP) controller. {Lecture}

Fabric Debug
Explains the fabric debug features available in the Versal device and reviews the different debug IP cores supported for Versal devices, such as the AXI Debug Hub, AXIS ILA, and AXIS VIO. {Lecture, Lab}

Hard Block Debug
Focuses on the debugging of Versal device hard blocks, such as the GTs, NoC, DDRMC, HBM, PCIe block, PS, and AI Engines. {Lecture}

Overview of HSDP
Describes the high-speed debug port (HSDP) in the Versal device. Also goes over the steps to use the SmartLynq+ module for high-speed debugging. {Lecture, Lab}

ChipScoPy Overview
Discusses the ChipScope hardware debug method and reviews how the ChipScoPy APIs are used for debugging the Versal device. {Lecture}

System Integration and Validation Methodology
Describes different simulation flows as well as timing and power closure techniques. Also explains how to improve system performance. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Designing with the Versal Adaptive SoC: Architecture
Familiarity with the Vivado Design Suite

RELATED COURSES:

Updated 08-29-2025

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