Designing with the Virtex-5 FPGA Family

Interested in learning how to effectively utilize Virtex-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Vivado Boot Camp: Basic Training and Designing for Performance, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.

Topics covered include a Virtex-5 FPGA overview, the CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. The resources available in the LXT and SXT platforms (EMAC, the PCI Express architecture, and GTP transceivers) are also discussed. In addition, you will learn about the resources included in the TXT and FXT platforms (GTX transceivers and the PowerPC processor). A combination of modules and labs allow for practical hands-on application of the principles taught.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the 6-input LUT of the Virtex-5 FPGA
  • Specify the CLB arrangement in the Virtex-5 FPGA
  • Define the block RAM resources of the Virtex-5 FPGA
  • Differentiate the arithmetic logic resources of the DSP48E slice in the Virtex-5 FPGA
  • Identify the clocking resources of the Virtex-5 FPGA
  • Describe the additional features of the Virtex-5 LXT, SXT, TXT, and FXT FPGA platforms

Course Outline

Day 1

  • Introduction
  • Virtex-5 FPGA Overview
  • CLB Resources
  • Clocking Resources
  • Lab 1: Clocking ResourcesIn this lab, you will use the Architecture Wizard to create a PLL core for instantiation in your design. You will then simulate and verify the PLL core.
  • I/O Resources
  • Memory Resources
  • XtremeDSP® Solution Resources
  • Lab 2: DSP48E Resourcesn this lab, you will create a MACC and a loadable MACC by using the XtremeDSP® solution (DSP48E) resource through the CORE Generator® software. You will then compare the OPMODEs chosen by the CORE Generator® software with the expected values.
  • Virtex-5 LXT, SXT, FXT, and TXT FPGA Overview
  • Lab 3: (Optional) DSP48E ResourcesThe DSP48E resource in the Virtex-5 FPGA can also be utilized to create non-DSP functions in order to save slice resources. In this optional lab, you will create a multiplexer by using the XtremeDSP® solution (DSP48E) resource through primitive instantiation. You will then simula

No Scheduled Sessions - Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
Standard Registration
9 Training Credits
Advanced Registration
Advanced Registration
8 Training Credits
Basic Follow-on Coaching
Comprehensive Follow-on Coaching
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

1 Day

Who should attend:

For those interested in Virtex-5 FPGA design training who have taken the Vivado Boot Camp: Basic Training and Designing for Performancecourses.


Vivado Boot Camp: Basic Training courseDesigning for Performance course

Software Tools

Xilinx ISE Design Suite: System Edition 11.1


Artix-7, Kintex-7, and Virtex-7 FPGAsDemo board: None* This course focuses on the 7 series FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626