Designing with Multi-Gigabit Serial I/O
Designing with Multi-Gigabit Serial I/O
Learn how to employ serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the 7 Series FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
After completing this comprehensive training, you will know how to:
- Describe and utilize the ports and attributes of the serial transceiver in 7 series FPGAs
- Effectively utilize the following features of the gigabit transceivers:8B/10B and other encoding/decoding, comma detection, clock correction, and channel bondingPre-emphasis and linear equalization
- Use the 7 Series FPGAs Transceivers Wizard to instantiate GT primitives in a design
- Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design
- 7 Series FPGAs Overview
- 7 Series FPGAs Transceivers Overview
- 7 Series FPGAs Transceivers Clocking and Resets
- 8B/10B Encoder and Decoder
- Lab 1: 8B/10B Encoding and BypassUtilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
- Commas and Deserializer Alignment
- Lab 2: Commas and Data AlignmentUse programmable comma detection to align a serial data stream.
- RX Elastic Buffer and Clock Correction
- Lab 3: Clock CorrectionUtilize the attributes and ports associated with clock correction to compensate for frequency differences on the TX and RX clocks.
- Channel Bonding
- Lab 4: Channel BondingModify a design to use two transceivers bonded together to form one virtual channel.
- Transceiver Wizard Overview
- Lab 5: Transceiver Core GenerationUse the 7 Series FPGAs Transceivers Wizard to create instantiation templates.
- Lab 6: SimulationSimulate the transceiver IP using the IP example design.
- Transceiver Implementation
- Lab 7: ImplementationImplement the transceiver IP using the IP example design.
- Physical Media Attachments
- 64B/66B Encoding and the GearboxImplement the transceiver IP using the IP example design.
- Lab 8: 64B/66B EncodingGenerate a 64B/66B core by using the 7 Series FPGAs Transceivers Wizard, simulate the design, and analyze the results.
- Transceiver Board Design Considerations
- Transceiver Test and Debugging
- Lab 9: Transceiver DebuggingDebug the transceiver IP using the IP example design and Vivado™ debug cores.
- Lab 10: IBERT LabCreate an IBERT design to verify physical links. (Choose Lab 10 or 11.)
- Lab 11: System LabPerform all design steps from planning the design, generating the core, integrating the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board. (Choose Lab 10 or 11.)
- Transceiver Application Examples
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Who should attend:
FPGA designers and logic designers
Familiarity with logic design (state machines and synchronous design)
Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Vivado™ System Edition 2015.1Mentor Graphics QuestaSim simulator 10.3d
Architecture: 7 series FPGAs*Demo board: Kintex-7 FPGA KC705 board** This course focuses on the Kintex-7 architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations