Vivado Boot Camp Phase-2: Implementing for Performance

This course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing and debugging the design. You will also build an effective FPGA design using synchronous design techniques, using the Vivado IP integrator to create a sub-system and using proper HDL coding techniques to improve design performance.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use the New Project Wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Create a Tcl script to create a project, add sources and implement a design
  • Use Tcl scripting in project and non-project batch flows to synthesize, implement and generate custom timing reports
  • Synthesize and implement the HDL design
  • Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
  • Generate a DRC report to detect and fix design issues early in the flow
  • Describe and use the clock resources in a design
  • Apply clock and I/O timing constraints and perform timing analysis
  • Use the Vivado IDE I/O Planning layout to perform pin assignments
  • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques and re-entrant mode as last mile strategies
  • Use the Vivado IP integrator to create a block design
  • Create and package your own IP and add to the Vivado IP catalog to reuse

Course Outline

Day 1

  • Introduction to Vivado Design Flows
  • Introduction to the TCL Environment
  • LAB: Introduction to the TCL Environment
  • Vivado Design Suite Project-Based Flow
  • LAB: Vivado Design Suite Project-Based Flow
  • Scripting in Vivado Design Suite Project Mode
  • LAB: Scripting in Vivado Design Suite Project Mode
  • Vivado Design Suite Non-Project Mode
  • Scripting in Vivado Design Suite Non-Project Mode
  • LAB: Scripting in Vivado Design Suite Non-Project Mode
  • Debugging and Error Management in TCL Scripting
  • Introduction to the Xilinx TCL Store
  • Demo: Introduction to the Xilinx TCL Store
  • Behavioral Simulation
  • Synthesis and Implementation
  • LAB: Synthesis and Implementation
  • Timing Simulation
  • LAB: Timing Simulation
  • LAB: Vivado Design Rules Checks

Day 2

  • Design Analysis Using TCL Commands
  • Demo: Design Analysis Using TCL Commands
  • LAB: Design Analysis Using TCL Commands
  • Incremental Compile Flow
  • LAB: Incremental Compile Flow
  • Physical Optimization
  • LAB: Physical Optimization
  • Introduction to Clock Constraints
  • Demo: Introduction to Clock Constraints
  • LAB: Introduction to Clock Constraints
  • Timing Constraints Editor
  • Timing Constraints Wizard
  • LAB: Timing Constraints Wizard
  • Report Clock Networks
  • Demo: Report Clock Networks
  • Vivado Design Suite I/O Pin Planning
  • LAB: Vivado Design Suite I/O Pin Planning
  • I/O Constraints and Virtual Clocks
  • LAB: I/O Constraints and Virtual Clocks
  • Demo: Basic Design Analysis in the Vivado IDE
  • LAB: Basic Design Analysis in the Vivado IDE

Day 3

  • Setup and Hold Timing Analysis
  • Introduction to Vivado Timing Reports
  • Demo: Introduction to Vivado Timing Reports
  • Timing Summary Report
  • Demo: Timing Summary Report
  • Vivado IP Flow
  • Demo: Vivado IP Flow
  • LAB: Vivado IP Flow
  • Creating and Packaging Custom IP
  • LAB: Creating and Packaging Custom IP
  • Using an IP Container
  • Demo: Using an IP Container
  • Designing with IP Integrator
  • Demo: Designing with IP Integrator
  • Case Study: Designing with IP Integrator
  • LAB: Designing with IP Integrator
  • Managing Remote IP
  • LAB: Managing Remote IP

Scheduled Classes

Your Facility / A Location near you
6/17/2019 - 6/19/2019
Parsippany, NJ
8/13/2019 - 8/15/2019
Trevose, PA
8/13/2019 - 8/15/2019
Hauppauge, NY
8/20/2019 - 8/22/2019
Your Facility / A Location near you
8/27/2019 - 8/29/2019
Rochester, NY
9/3/2019 - 9/5/2019
Sterling, Virginia
10/1/2019 - 10/3/2019
Columbia, MD
10/15/2019 - 10/17/2019

Education Investment Options

Standard Registration
$2,700
Standard Registration
27 Training Credits
Advanced Registration
$2,400
Advanced Registration
24 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

3 Days

Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with Xilinx FPGAs.

Prerequisites

Version: 2019-07-15_1607