Course Description

This course provides hardware and firmware engineers with the knowledge to effectively utilize a Zynq All Programmable System on a Chip (SoC). It covers the architecture of the ARM™ Cortex®-A9 processor-based processing system (PS) and the integration of programmable logic (PL).

The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Training Duration

Who Should Attend?

Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq™ All Programmable SoC and programmable logic.

Prerequisites

• FPGA design experience
• Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx Vivado™ software implementation tools
• Basic understanding of C programming
• Basic understanding of microprocessors
• Some HDL modeling experience

Hardware

• Architecture: Zynq-7000 All Programmable SoC*
• Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

• Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
• Evaluate a processing system (PS) and programmable logic (PL) AXI interface
• Identify the configuration options for the Zynq All Programmable SoC

Course Outline

Day 1

1. Zynq All Programmable SoC Overview
   
2. Inside the Application Processor Unit (APU)
   
3. Processor Input/Output Peripherals
   
4. Lab 1: Building a Zynq All Programmable SoC Platform
   Examine the process of using the Vivado IP Integrator tool to create a simple processing system.
5. Zynq All Programmable SoC PS/PL Interface
   
6. Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC
   Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.
7. Lab 3: Impact of Port Selection on System Performance
   Explore bandwidth issues surrounding the use of the Accelerator Coherency Port (ACP) and the High Performance (HP) ports.
8. Zynq All Programmable SoC Booting
   
9. Zynq All Programmable SoC Memory Resources
   
10. Lab 4: Running and Debugging a Linux Application on the Zynq All Programmable SoC
    Explore a software application executing under the Linux operating system on the Zynq All Programmable SoC.

Scheduled Classes

Education Investment Options

• To qualify for the Advanced Registration Price,
  full payment must be received 21 days prior to the first day of class.
• Basic follow-on coaching includes 2 hours (max 2 calls)
• Comprehensive follow-on coaching includes 10 hours (max 5 calls).
• Follow-on Coaching must be purchased at time of registration.